ex10sch.rpt
来自「[VHDL经典设计26例]--在xilinx芯片上调试通过--[01--1位全加」· RPT 代码 · 共 620 行 · 第 1/3 页
RPT
620 行
\$Net00009_ 2 0 0 3 FB3_10 STD 40 I/O O
\$Net00047_ 2 0 0 3 FB3_11 STD 33 I/O O
\$Net00046_ 2 0 0 3 FB3_12 STD 41 I/O O
\$Net00042_ 2 0 0 3 FB3_13 STD 43 I/O O
&__A__9 4 0 0 1 FB3_14 STD 36 I/O (b)
&__A__13 4 0 0 1 FB3_15 STD 37 I/O (b)
\$Net00041_ 2 0 0 3 FB3_16 STD 45 I/O O
&__A__15 5 0 0 0 FB3_17 STD 39 I/O (b)
&__A__11 5 0 0 0 FB3_18 STD (b) (b)
Signals Used by Logic in Function Block
1: "&__A__10.FBK".LFBK
6: "&__A__15.FBK".LFBK
11: "\$Net00002_"
2: "&__A__11.FBK".LFBK
7: "&__A__16.FBK".LFBK
12: "\$Net00005_.FBK".LFBK
3: "&__A__12.FBK".LFBK
8: "&__A__7" 13: "\$Net00006_.FBK".LFBK
4: "&__A__13.FBK".LFBK
9: "&__A__8" 14: CLK
5: "&__A__14.FBK".LFBK
10: "&__A__9.FBK".LFBK
15: UCLK
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
&__A__6 .......XX.XX.X.......................... 5 5
&__A__16 ..........X..XX......................... 3 3
&__A__14 .....XX...X..XX......................... 5 5
&__A__12 ..........X.XX.......................... 3 3
&__A__10 .XX.......X.XX.......................... 5 5
\$Net00006_ ...XXXX...X.XXX......................... 8 8
\$Net00005_ XXX......XXXXX.......................... 8 8
\$Net00009_ ......X...X............................. 2 2
\$Net00047_ ....X.....X............................. 2 2
\$Net00046_ .....X....X............................. 2 2
\$Net00042_ ...X......X............................. 2 2
&__A__9 XXX......XX.XX.......................... 7 7
&__A__13 ...XXXX...X..XX......................... 7 7
\$Net00041_ .X........X............................. 2 2
&__A__15 ...XXXX...X..XX......................... 7 7
&__A__11 XXX......XX.XX.......................... 7 7
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK/FCLK - Global clock
O - Output GTS/FOE - Global 3state/output-enable
(b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB4 ***********************************
Number of function block inputs used/remaining: 15/21
Number of signals used by logic mapping into function block: 15
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
\$Net00043_ 2 0 0 3 FB4_1 STD 46 I/O O
\$Net00044_ 2 0 0 3 FB4_2 STD 44 I/O O
\$Net00051_ 2 0 0 3 FB4_3 STD 51 I/O O
\$Net00039_ 2 0 0 3 FB4_4 STD 52 I/O O
\$Net00045_ 2 0 0 3 FB4_5 STD 47 I/O O
\$Net00038_ 2 0 0 3 FB4_6 STD 54 I/O O
\$Net00040_ 2 0 0 3 FB4_7 STD 55 I/O O
(unused) 0 0 0 5 FB4_8 48 I/O
\$Net00049_ 2 0 0 3 FB4_9 STD 50 I/O O
\$Net00050_ 2 0 0 3 FB4_10 STD 57 I/O O
\$Net00037_ 2 0 0 3 FB4_11 STD 53 I/O O
\$Net00048_ 2 0 0 3 FB4_12 STD 58 I/O O
(unused) 0 0 0 5 FB4_13 61 I/O
\$Net00004_ 4 0 0 1 FB4_14 STD 56 I/O (b)
&__A__5 4 0 0 1 FB4_15 STD 65 I/O (b)
&__A__1 4 0 0 1 FB4_16 STD 62 I/O (b)
&__A__7 5 0 0 0 FB4_17 STD 66 I/O (b)
&__A__3 5 0 0 0 FB4_18 STD (b) (b)
Signals Used by Logic in Function Block
1: "&__A__1.FBK".LFBK
6: "&__A__4" 11: "&__A__9"
2: "&__A__10" 7: "&__A__5.FBK".LFBK
12: "\$Net00002_"
3: "&__A__12" 8: "&__A__6" 13: "\$Net00004_.FBK".LFBK
4: "&__A__2" 9: "&__A__7.FBK".LFBK
14: "\$Net00005_"
5: "&__A__3.FBK".LFBK
10: "&__A__8" 15: CLK
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
\$Net00043_ .X.........X............................ 2 2
\$Net00044_ ..X........X............................ 2 2
\$Net00051_ ......X....X............................ 2 2
\$Net00039_ .....X.....X............................ 2 2
\$Net00045_ ..........XX............................ 2 2
\$Net00038_ ...X.......X............................ 2 2
\$Net00040_ X..........X............................ 2 2
\$Net00049_ .......X...X............................ 2 2
\$Net00050_ .........X.X............................ 2 2
\$Net00037_ ....X......X............................ 2 2
\$Net00048_ ........X..X............................ 2 2
\$Net00004_ ......XXXX.XXXX......................... 8 8
&__A__5 ......XXXX.X.XX......................... 7 7
&__A__1 X..XXX.....XX.X......................... 7 7
&__A__7 ......XXXX.X.XX......................... 7 7
&__A__3 X..XXX.....XX.X......................... 7 7
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK/FCLK - Global clock
O - Output GTS/FOE - Global 3state/output-enable
(b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
;;-----------------------------------------------------------------;;
; Implemented Equations.
"&__A__1".T = "&__A__4" * "&__A__2" * "\$Net00002_" *
"&__A__3.FBK".LFBK
+ "&__A__4" * /"&__A__2" * "\$Net00002_" *
/"&__A__3.FBK".LFBK * "&__A__1.FBK".LFBK
"&__A__1".CLKF = "\$Net00004_.FBK".LFBK
"&__A__1".RSTF = /CLK * /"\$Net00002_"
"&__A__1".PRLD = GND
"&__A__10".T = "\$Net00002_" * "&__A__12.FBK".LFBK *
"&__A__11.FBK".LFBK
"&__A__10".CLKF = "\$Net00006_.FBK".LFBK
"&__A__10".RSTF = /CLK * /"\$Net00002_"
"&__A__10".PRLD = GND
"&__A__11".T = "\$Net00002_" * "&__A__12.FBK".LFBK *
"&__A__10.FBK".LFBK
+ "\$Net00002_" * "&__A__12.FBK".LFBK *
/"&__A__9.FBK".LFBK
+ "\$Net00002_" * "&__A__12.FBK".LFBK *
"&__A__11.FBK".LFBK
"&__A__11".CLKF = "\$Net00006_.FBK".LFBK
"&__A__11".RSTF = /CLK * /"\$Net00002_"
"&__A__11".PRLD = GND
"&__A__12".T = "\$Net00002_"
"&__A__12".CLKF = "\$Net00006_.FBK".LFBK
"&__A__12".RSTF = /CLK * /"\$Net00002_"
"&__A__12".PRLD = GND
"&__A__13".T = "\$Net00002_" * "&__A__16.FBK".LFBK *
"&__A__15.FBK".LFBK * "&__A__14.FBK".LFBK
+ "\$Net00002_" * "&__A__16.FBK".LFBK *
/"&__A__15.FBK".LFBK * /"&__A__14.FBK".LFBK * "&__A__13.FBK".LFBK
"&__A__13".CLKF = UCLK
"&__A__13".RSTF = /CLK * /"\$Net00002_"
"&__A__13".PRLD = GND
"&__A__14".T = "\$Net00002_" * "&__A__16.FBK".LFBK *
"&__A__15.FBK".LFBK
"&__A__14".CLKF = UCLK
"&__A__14".RSTF = /CLK * /"\$Net00002_"
"&__A__14".PRLD = GND
/"&__A__15".T = /"\$Net00002_"
+ /"&__A__16.FBK".LFBK
+ /"&__A__15.FBK".LFBK * /"&__A__14.FBK".LFBK *
"&__A__13.FBK".LFBK
"&__A__15".CLKF = UCLK
"&__A__15".RSTF = /CLK * /"\$Net00002_"
"&__A__15".PRLD = GND
"&__A__16".T = "\$Net00002_"
"&__A__16".CLKF = UCLK
"&__A__16".RSTF = /CLK * /"\$Net00002_"
"&__A__16".PRLD = GND
"&__A__2".T = "&__A__3" * "\$Net00002_.FBK".LFBK *
"&__A__4.FBK".LFBK
"&__A__2".CLKF = "\$Net00004_"
"&__A__2".RSTF = /CLK * /"\$Net00002_.FBK".LFBK
"&__A__2".PRLD = GND
/"&__A__3".T = /"&__A__4"
+ /"\$Net00002_"
+ /"&__A__2" * /"&__A__3.FBK".LFBK *
"&__A__1.FBK".LFBK
"&__A__3".CLKF = "\$Net00004_.FBK".LFBK
"&__A__3".RSTF = /CLK * /"\$Net00002_"
"&__A__3".PRLD = GND
"&__A__4".T = "\$Net00002_.FBK".LFBK
"&__A__4".CLKF = "\$Net00004_"
"&__A__4".RSTF = /CLK * /"\$Net00002_.FBK".LFBK
"&__A__4".PRLD = GND
"&__A__5".T = "&__A__8" * "&__A__6" * "\$Net00002_" *
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