ex10sch.rpt
来自「[VHDL经典设计26例]--在xilinx芯片上调试通过--[01--1位全加」· RPT 代码 · 共 620 行 · 第 1/3 页
RPT
620 行
cpldfit: version E.38 Xilinx Inc.
Fitter Report
Design Name: ex10sch Date: 3-15-2008, 1:18AM
Device Used: XC9572-10-PC84
Fitting Status: Successful
**************************** Resource Summary ****************************
Macrocells Product Terms Registers Pins Function Block
Used Used Used Used Inputs Used
36 /72 ( 50%) 106 /360 ( 29%) 36 /72 ( 50%) 18 /69 ( 26%) 36 /144 ( 25%)
PIN RESOURCES:
Signal Type Required Mapped | Pin Type Used Remaining
------------------------------------|---------------------------------------
Input : 2 2 | I/O : 18 45
Output : 16 16 | GCK/IO : 0 3
Bidirectional : 0 0 | GTS/IO : 0 2
GCK : 0 0 | GSR/IO : 0 1
GTS : 0 0 |
GSR : 0 0 |
---- ----
Total 18 18
MACROCELL RESOURCES:
Total Macrocells Available 72
Registered Macrocells 36
Non-registered Macrocell driving I/O 0
GLOBAL RESOURCES:
Global clock net(s) unused.
Global output enable net(s) unused.
Global set/reset net(s) unused.
POWER DATA:
There are 36 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
There are a total of 36 macrocells used (MC).
End of Resource Summary
***************Resources Used by Successfully Mapped Logic******************
** LOGIC **
Signal Total Signals Loc Pwr Slew Pin Pin Pin
Name Pt Used Mode Rate # Type Use
&__A__1 4 7 FB4_16 STD 62 I/O (b)
&__A__10 3 5 FB3_7 STD 35 I/O (b)
&__A__11 5 7 FB3_18 STD (b) (b)
&__A__12 3 3 FB3_6 STD 34 I/O (b)
&__A__13 4 7 FB3_15 STD 37 I/O (b)
&__A__14 3 5 FB3_5 STD 19 I/O (b)
&__A__15 5 7 FB3_17 STD 39 I/O (b)
&__A__16 3 3 FB3_4 STD 32 I/O I
&__A__2 3 5 FB1_18 STD 24 I/O (b)
&__A__3 5 7 FB4_18 STD (b) (b)
&__A__4 3 3 FB1_17 STD 15 I/O (b)
&__A__5 4 7 FB4_15 STD 65 I/O (b)
&__A__6 3 5 FB3_3 STD 31 I/O I
&__A__7 5 7 FB4_17 STD 66 I/O (b)
&__A__8 3 3 FB1_16 STD 23 I/O (b)
&__A__9 4 7 FB3_14 STD 36 I/O (b)
\$Net00002_ 2 2 FB1_15 STD 14 I/O (b)
\$Net00004_ 4 8 FB4_14 STD 56 I/O (b)
\$Net00005_ 4 8 FB3_9 STD 26 I/O (b)
\$Net00006_ 4 8 FB3_8 STD 21 I/O (b)
\$Net00009_ 2 2 FB3_10 STD FAST 40 I/O O
\$Net00037_ 2 2 FB4_11 STD FAST 53 I/O O
\$Net00038_ 2 2 FB4_6 STD FAST 54 I/O O
\$Net00039_ 2 2 FB4_4 STD FAST 52 I/O O
\$Net00040_ 2 2 FB4_7 STD FAST 55 I/O O
\$Net00041_ 2 2 FB3_16 STD FAST 45 I/O O
\$Net00042_ 2 2 FB3_13 STD FAST 43 I/O O
\$Net00043_ 2 2 FB4_1 STD FAST 46 I/O O
\$Net00044_ 2 2 FB4_2 STD FAST 44 I/O O
\$Net00045_ 2 2 FB4_5 STD FAST 47 I/O O
\$Net00046_ 2 2 FB3_12 STD FAST 41 I/O O
\$Net00047_ 2 2 FB3_11 STD FAST 33 I/O O
\$Net00048_ 2 2 FB4_12 STD FAST 58 I/O O
\$Net00049_ 2 2 FB4_9 STD FAST 50 I/O O
\$Net00050_ 2 2 FB4_10 STD FAST 57 I/O O
\$Net00051_ 2 2 FB4_3 STD FAST 51 I/O O
** INPUTS **
Signal Loc Pin Pin Pin
Name # Type Use
CLK FB3_4 32 I/O I
UCLK FB3_3 31 I/O I
End of Resources Used by Successfully Mapped Logic
*********************Function Block Resource Summary***********************
Function # of FB Inputs Signals Total O/IO IO
Block Macrocells Used Used Pt Used Req Avail
FB1 4 6 6 11 0/0 18
FB2 0 0 0 0 0/0 17
FB3 16 15 15 51 5/0 17
FB4 16 15 15 44 11/0 17
---- ----- ----- -----
36 106 16/0 69
*********************************** FB1 ***********************************
Number of function block inputs used/remaining: 6/30
Number of signals used by logic mapping into function block: 6
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB1_1 4 I/O
(unused) 0 0 0 5 FB1_2 1 I/O
(unused) 0 0 0 5 FB1_3 6 I/O
(unused) 0 0 0 5 FB1_4 7 I/O
(unused) 0 0 0 5 FB1_5 2 I/O
(unused) 0 0 0 5 FB1_6 3 I/O
(unused) 0 0 0 5 FB1_7 11 I/O
(unused) 0 0 0 5 FB1_8 5 I/O
(unused) 0 0 0 5 FB1_9 9 GCK/I/O
(unused) 0 0 0 5 FB1_10 13 I/O
(unused) 0 0 0 5 FB1_11 10 GCK/I/O
(unused) 0 0 0 5 FB1_12 18 I/O
(unused) 0 0 0 5 FB1_13 20 I/O
(unused) 0 0 0 5 FB1_14 12 GCK/I/O
\$Net00002_ 2 0 0 3 FB1_15 STD 14 I/O (b)
&__A__8 3 0 0 2 FB1_16 STD 23 I/O (b)
&__A__4 3 0 0 2 FB1_17 STD 15 I/O (b)
&__A__2 3 0 0 2 FB1_18 STD 24 I/O (b)
Signals Used by Logic in Function Block
1: "&__A__3" 3: "\$Net00002_.FBK".LFBK
5: "\$Net00005_"
2: "&__A__4.FBK".LFBK
4: "\$Net00004_" 6: CLK
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
\$Net00002_ ..X..X.................................. 2 2
&__A__8 ..X.XX.................................. 3 3
&__A__4 ..XX.X.................................. 3 3
&__A__2 XXXX.X.................................. 5 5
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK/FCLK - Global clock
O - Output GTS/FOE - Global 3state/output-enable
(b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB2 ***********************************
Number of function block inputs used/remaining: 0/36
Number of signals used by logic mapping into function block: 0
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB2_1 63 I/O
(unused) 0 0 0 5 FB2_2 69 I/O
(unused) 0 0 0 5 FB2_3 67 I/O
(unused) 0 0 0 5 FB2_4 68 I/O
(unused) 0 0 0 5 FB2_5 70 I/O
(unused) 0 0 0 5 FB2_6 71 I/O
(unused) 0 0 0 5 FB2_7 76 GTS/I/O
(unused) 0 0 0 5 FB2_8 72 I/O
(unused) 0 0 0 5 FB2_9 74 GSR/I/O
(unused) 0 0 0 5 FB2_10 75 I/O
(unused) 0 0 0 5 FB2_11 77 GTS/I/O
(unused) 0 0 0 5 FB2_12 79 I/O
(unused) 0 0 0 5 FB2_13 80 I/O
(unused) 0 0 0 5 FB2_14 81 I/O
(unused) 0 0 0 5 FB2_15 83 I/O
(unused) 0 0 0 5 FB2_16 82 I/O
(unused) 0 0 0 5 FB2_17 84 I/O
(unused) 0 0 0 5 FB2_18 (b)
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK/FCLK - Global clock
O - Output GTS/FOE - Global 3state/output-enable
(b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB3 ***********************************
Number of function block inputs used/remaining: 15/21
Number of signals used by logic mapping into function block: 15
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB3_1 25 I/O
(unused) 0 0 0 5 FB3_2 17 I/O
&__A__6 3 0 0 2 FB3_3 STD 31 I/O I
&__A__16 3 0 0 2 FB3_4 STD 32 I/O I
&__A__14 3 0 0 2 FB3_5 STD 19 I/O (b)
&__A__12 3 0 0 2 FB3_6 STD 34 I/O (b)
&__A__10 3 0 0 2 FB3_7 STD 35 I/O (b)
\$Net00006_ 4 0 0 1 FB3_8 STD 21 I/O (b)
\$Net00005_ 4 0 0 1 FB3_9 STD 26 I/O (b)
⌨️ 快捷键说明
复制代码Ctrl + C
搜索代码Ctrl + F
全屏模式F11
增大字号Ctrl + =
减小字号Ctrl + -
显示快捷键?