ex25.mfd

来自「[VHDL经典设计26例]--在xilinx芯片上调试通过--[01--1位全加」· MFD 代码 · 共 1,250 行 · 第 1/5 页
MFD
1,250 行
EQ | 35 | 
    "txd_shift<4>".T  =  "txd_cnt<2>" * "txcnt16<1>" * "txcnt16<0>" * 
	"txcnt16<2>.FBK".LFBK * "txcnt16<3>.FBK".LFBK * "txd_shift<4>.FBK".LFBK * 
	/"txd_shift<5>.FBK".LFBK
	+ "txd_cnt<2>" * "txcnt16<1>" * "txcnt16<0>" * 
	"txcnt16<2>.FBK".LFBK * "txcnt16<3>.FBK".LFBK * /"txd_shift<4>.FBK".LFBK * 
	"txd_shift<5>.FBK".LFBK
	+ "txd_cnt<1>" * /"txd_cnt<3>" * "txcnt16<1>" * 
	"txcnt16<0>" * "txcnt16<2>.FBK".LFBK * "txcnt16<3>.FBK".LFBK * 
	"txd_shift<4>.FBK".LFBK * /"txd_shift<5>.FBK".LFBK
;Imported pterms FB1_9
	+ /"txd_cnt<1>" * "txd_cnt<3>" * "txcnt16<1>" * 
	"txcnt16<0>" * "txcnt16<2>.FBK".LFBK * "txcnt16<3>.FBK".LFBK * 
	"txd_shift<4>.FBK".LFBK * /"txd_shift<5>.FBK".LFBK
	+ "txd_cnt<3>" * "txcnt16<1>" * "txcnt16<0>" * 
	"txd_cnt<0>.FBK".LFBK * "txcnt16<2>.FBK".LFBK * "txcnt16<3>.FBK".LFBK * 
	"txd_shift<4>.FBK".LFBK * /"txd_shift<5>.FBK".LFBK
;Imported pterms FB1_11
	+ "txd_cnt<1>" * /"txd_cnt<3>" * "txcnt16<1>" * 
	"txcnt16<0>" * "txcnt16<2>.FBK".LFBK * "txcnt16<3>.FBK".LFBK * 
	/"txd_shift<4>.FBK".LFBK * "txd_shift<5>.FBK".LFBK
	+ /"txd_cnt<1>" * "txd_cnt<3>" * "txcnt16<1>" * 
	"txcnt16<0>" * "txcnt16<2>.FBK".LFBK * "txcnt16<3>.FBK".LFBK * 
	/"txd_shift<4>.FBK".LFBK * "txd_shift<5>.FBK".LFBK
	+ "txd_cnt<3>" * "txcnt16<1>" * "txcnt16<0>" * 
	"txd_cnt<0>.FBK".LFBK * "txcnt16<2>.FBK".LFBK * "txcnt16<3>.FBK".LFBK * 
	/"txd_shift<4>.FBK".LFBK * "txd_shift<5>.FBK".LFBK
	+ /"txd_cnt<1>" * /"txd_cnt<2>" * /"txd_cnt<3>" * 
	"txcnt16<1>" * "txcnt16<0>" * "tbuf<4>" * "txd_cnt<0>.FBK".LFBK * 
	"txcnt16<2>.FBK".LFBK * "txcnt16<3>.FBK".LFBK * /"txd_shift<4>.FBK".LFBK
	+ /"txd_cnt<1>" * /"txd_cnt<2>" * /"txd_cnt<3>" * 
	"txcnt16<1>" * "txcnt16<0>" * /"tbuf<4>" * "txd_cnt<0>.FBK".LFBK * 
	"txcnt16<2>.FBK".LFBK * "txcnt16<3>.FBK".LFBK * "txd_shift<4>.FBK".LFBK
    "txd_shift<4>".CLKF  =  bclk.PIN
    "txd_shift<4>".RSTF  =  rst
    "txd_shift<4>".PRLD  =  GND

MACROCELL | 0 | 6 | txd_shift<5>
ATTRIBUTES | 4391728 | 0
OUTPUTMC | 7 | 0 | 8 | 0 | 9 | 0 | 6 | 0 | 4 | 0 | 7 | 0 | 5 | 0 | 10
INPUTS | 13 | txd_cnt<2>  | txcnt16<1>  | txcnt16<0>  | txcnt16<3>.FBK".LFBK  | txd_shift<5>.FBK".LFBK  | txd_shift<6>.FBK".LFBK  | bclk.PIN  | txd_cnt<1>  | txd_cnt<3>  | EXP2_.EXP  | txd_shift<7>.EXP  | rst  | txcnt16<2>.FBK".LFBK
INPUTMC | 11 | 3 | 1 | 2 | 11 | 2 | 12 | 0 | 8 | 0 | 6 | 0 | 4 | 3 | 7 | 3 | 6 | 0 | 5 | 0 | 7 | 0 | 0
INPUTP | 2 | 77 | 32
IMPORTS | 2 | 0 | 5 | 0 | 7
EQ | 36 | 
    "txd_shift<5>".T  =  "txd_cnt<2>" * "txcnt16<1>" * "txcnt16<0>" * 
	"txcnt16<2>.FBK".LFBK * "txcnt16<3>.FBK".LFBK * "txd_shift<6>.FBK".LFBK * 
	/"txd_shift<5>.FBK".LFBK
	+ "txd_cnt<2>" * "txcnt16<1>" * "txcnt16<0>" * 
	"txcnt16<2>.FBK".LFBK * "txcnt16<3>.FBK".LFBK * /"txd_shift<6>.FBK".LFBK * 
	"txd_shift<5>.FBK".LFBK
	+ "txd_cnt<1>" * /"txd_cnt<3>" * "txcnt16<1>" * 
	"txcnt16<0>" * "txcnt16<2>.FBK".LFBK * "txcnt16<3>.FBK".LFBK * 
	/"txd_shift<6>.FBK".LFBK * "txd_shift<5>.FBK".LFBK
;Imported pterms FB1_6
	+ "txd_cnt<1>" * /"txd_cnt<3>" * "txcnt16<1>" * 
	"txcnt16<0>" * "txcnt16<2>.FBK".LFBK * "txcnt16<3>.FBK".LFBK * 
	"txd_shift<6>.FBK".LFBK * /"txd_shift<5>.FBK".LFBK
	+ /"txd_cnt<1>" * "txd_cnt<3>" * "txcnt16<1>" * 
	"txcnt16<0>" * "txcnt16<2>.FBK".LFBK * "txcnt16<3>.FBK".LFBK * 
	"txd_shift<6>.FBK".LFBK * /"txd_shift<5>.FBK".LFBK
	+ /"txd_cnt<1>" * "txd_cnt<3>" * "txcnt16<1>" * 
	"txcnt16<0>" * "txcnt16<2>.FBK".LFBK * "txcnt16<3>.FBK".LFBK * 
	/"txd_shift<6>.FBK".LFBK * "txd_shift<5>.FBK".LFBK
	+ "txd_cnt<3>" * "txcnt16<1>" * "txcnt16<0>" * 
	"txd_cnt<0>.FBK".LFBK * "txcnt16<2>.FBK".LFBK * "txcnt16<3>.FBK".LFBK * 
	"txd_shift<6>.FBK".LFBK * /"txd_shift<5>.FBK".LFBK
	+ "txd_cnt<3>" * "txcnt16<1>" * "txcnt16<0>" * 
	"txd_cnt<0>.FBK".LFBK * "txcnt16<2>.FBK".LFBK * "txcnt16<3>.FBK".LFBK * 
	/"txd_shift<6>.FBK".LFBK * "txd_shift<5>.FBK".LFBK
;Imported pterms FB1_5
	+ /"txd_cnt<1>" * /"txd_cnt<2>" * /"txd_cnt<3>" * 
	"txcnt16<1>" * "txcnt16<0>" * "tbuf<5>" * "txd_cnt<0>.FBK".LFBK * 
	"txcnt16<2>.FBK".LFBK * "txcnt16<3>.FBK".LFBK * /"txd_shift<5>.FBK".LFBK
;Imported pterms FB1_8
	+ /"txd_cnt<1>" * /"txd_cnt<2>" * /"txd_cnt<3>" * 
	"txcnt16<1>" * "txcnt16<0>" * /"tbuf<5>" * "txd_cnt<0>.FBK".LFBK * 
	"txcnt16<2>.FBK".LFBK * "txcnt16<3>.FBK".LFBK * "txd_shift<5>.FBK".LFBK
    "txd_shift<5>".CLKF  =  bclk.PIN
    "txd_shift<5>".RSTF  =  rst
    "txd_shift<5>".PRLD  =  GND

MACROCELL | 0 | 4 | txd_shift<6>
ATTRIBUTES | 4391728 | 0
OUTPUTMC | 5 | 0 | 5 | 0 | 2 | 0 | 6 | 0 | 4 | 0 | 3
INPUTS | 15 | txd_cnt<2>  | txcnt16<1>  | txcnt16<0>  | txcnt16<3>.FBK".LFBK  | txd_shift<6>.FBK".LFBK  | txd_shift<7>.FBK".LFBK  | txd_cnt<0>.FBK".LFBK  | txd_shift<5>.FBK".LFBK  | txd_cnt<1>  | txd_cnt<3>  | bclk.PIN  | rst  | tbuf<5>  | EXP1_.EXP  | txcnt16<2>.FBK".LFBK
INPUTMC | 12 | 3 | 1 | 2 | 11 | 2 | 12 | 0 | 8 | 0 | 4 | 0 | 7 | 0 | 2 | 0 | 6 | 3 | 7 | 3 | 6 | 0 | 3 | 0 | 0
INPUTP | 3 | 77 | 32 | 52
EXPORTS | 1 | 0 | 5
IMPORTS | 1 | 0 | 3
EQ | 38 | 
    "txd_shift<6>".T  =  "txd_cnt<2>" * "txcnt16<1>" * "txcnt16<0>" * 
	"txcnt16<2>.FBK".LFBK * "txcnt16<3>.FBK".LFBK * "txd_shift<6>.FBK".LFBK * 
	/"txd_shift<7>.FBK".LFBK
	+ "txd_cnt<2>" * "txcnt16<1>" * "txcnt16<0>" * 
	"txcnt16<2>.FBK".LFBK * "txcnt16<3>.FBK".LFBK * /"txd_shift<6>.FBK".LFBK * 
	"txd_shift<7>.FBK".LFBK
;Imported pterms FB1_4
	+ "txd_cnt<1>" * /"txd_cnt<3>" * "txcnt16<1>" * 
	"txcnt16<0>" * "txcnt16<2>.FBK".LFBK * "txcnt16<3>.FBK".LFBK * 
	"txd_shift<6>.FBK".LFBK * /"txd_shift<7>.FBK".LFBK
	+ "txd_cnt<1>" * /"txd_cnt<3>" * "txcnt16<1>" * 
	"txcnt16<0>" * "txcnt16<2>.FBK".LFBK * "txcnt16<3>.FBK".LFBK * 
	/"txd_shift<6>.FBK".LFBK * "txd_shift<7>.FBK".LFBK
	+ /"txd_cnt<1>" * "txd_cnt<3>" * "txcnt16<1>" * 
	"txcnt16<0>" * "txcnt16<2>.FBK".LFBK * "txcnt16<3>.FBK".LFBK * 
	"txd_shift<6>.FBK".LFBK * /"txd_shift<7>.FBK".LFBK
	+ /"txd_cnt<1>" * "txd_cnt<3>" * "txcnt16<1>" * 
	"txcnt16<0>" * "txcnt16<2>.FBK".LFBK * "txcnt16<3>.FBK".LFBK * 
	/"txd_shift<6>.FBK".LFBK * "txd_shift<7>.FBK".LFBK
	+ "txd_cnt<3>" * "txcnt16<1>" * "txcnt16<0>" * 
	"txd_cnt<0>.FBK".LFBK * "txcnt16<2>.FBK".LFBK * "txcnt16<3>.FBK".LFBK * 
	"txd_shift<6>.FBK".LFBK * /"txd_shift<7>.FBK".LFBK
;Imported pterms FB1_3
	+ "txd_cnt<3>" * "txcnt16<1>" * "txcnt16<0>" * 
	"txd_cnt<0>.FBK".LFBK * "txcnt16<2>.FBK".LFBK * "txcnt16<3>.FBK".LFBK * 
	/"txd_shift<6>.FBK".LFBK * "txd_shift<7>.FBK".LFBK
	+ /"txd_cnt<1>" * /"txd_cnt<2>" * /"txd_cnt<3>" * 
	"txcnt16<1>" * "txcnt16<0>" * "tbuf<6>" * "txd_cnt<0>.FBK".LFBK * 
	"txcnt16<2>.FBK".LFBK * "txcnt16<3>.FBK".LFBK * /"txd_shift<6>.FBK".LFBK
	+ /"txd_cnt<1>" * /"txd_cnt<2>" * /"txd_cnt<3>" * 
	"txcnt16<1>" * "txcnt16<0>" * /"tbuf<6>" * "txd_cnt<0>.FBK".LFBK * 
	"txcnt16<2>.FBK".LFBK * "txcnt16<3>.FBK".LFBK * "txd_shift<6>.FBK".LFBK
    "txd_shift<6>".CLKF  =  bclk.PIN
    "txd_shift<6>".RSTF  =  rst
    "txd_shift<6>".PRLD  =  GND
    txd_shift<6>.EXP  =  /"txd_cnt<1>" * /"txd_cnt<2>" * /"txd_cnt<3>" * 
	"txcnt16<1>" * "txcnt16<0>" * "tbuf<5>" * "txd_cnt<0>.FBK".LFBK * 
	"txcnt16<2>.FBK".LFBK * "txcnt16<3>.FBK".LFBK * /"txd_shift<5>.FBK".LFBK

MACROCELL | 0 | 7 | txd_shift<7>
ATTRIBUTES | 4391728 | 0
OUTPUTMC | 5 | 0 | 6 | 0 | 2 | 0 | 4 | 0 | 7 | 0 | 3
INPUTS | 14 | txcnt16<2>.FBK".LFBK  | txd_cnt<1>  | txd_cnt<2>  | txd_cnt<3>  | txcnt16<1>  | txcnt16<0>  | txcnt16<3>.FBK".LFBK  | txd_shift<7>.FBK".LFBK  | txd_shift<5>.FBK".LFBK  | tbuf<7>  | rst  | bclk.PIN  | tbuf<5>  | txd_cnt<0>.FBK".LFBK
INPUTMC | 10 | 0 | 0 | 3 | 7 | 3 | 1 | 3 | 6 | 2 | 11 | 2 | 12 | 0 | 8 | 0 | 7 | 0 | 6 | 0 | 2
INPUTP | 4 | 57 | 32 | 77 | 52
EXPORTS | 1 | 0 | 6
EQ | 12 | 
    "txd_shift<7>".T  =  /"txd_cnt<1>" * /"txd_cnt<2>" * /"txd_cnt<3>" * 
	"txcnt16<1>" * "txcnt16<0>" * "tbuf<7>" * "txd_cnt<0>.FBK".LFBK * 
	"txcnt16<2>.FBK".LFBK * "txcnt16<3>.FBK".LFBK * /"txd_shift<7>.FBK".LFBK
	+ /"txd_cnt<1>" * /"txd_cnt<2>" * /"txd_cnt<3>" * 
	"txcnt16<1>" * "txcnt16<0>" * /"tbuf<7>" * "txd_cnt<0>.FBK".LFBK * 
	"txcnt16<2>.FBK".LFBK * "txcnt16<3>.FBK".LFBK * "txd_shift<7>.FBK".LFBK
    "txd_shift<7>".CLKF  =  bclk.PIN
    "txd_shift<7>".RSTF  =  rst
    "txd_shift<7>".PRLD  =  GND
    txd_shift<7>.EXP  =  /"txd_cnt<1>" * /"txd_cnt<2>" * /"txd_cnt<3>" * 
	"txcnt16<1>" * "txcnt16<0>" * /"tbuf<5>" * "txd_cnt<0>.FBK".LFBK * 
	"txcnt16<2>.FBK".LFBK * "txcnt16<3>.FBK".LFBK * "txd_shift<5>.FBK".LFBK

MACROCELL | 3 | 16 | N_rbuf<0>
ATTRIBUTES | 4653858 | 0
OUTPUTMC | 2 | 3 | 17 | 3 | 15
INPUTS | 11 | txd_cnt<0>  | txd_shift<0>.FBK".LFBK  | txcnt16<1>  | txcnt16<0>  | txcnt16<2>  | txcnt16<3>  | txd_cnt<1>.FBK".LFBK  | txd_shift<1>  | N_bclk.FBK.LFBK  | N_xmit_done.EXP  | txd_cnt<3>.FBK".LFBK
INPUTMC | 11 | 0 | 2 | 3 | 17 | 2 | 11 | 2 | 12 | 0 | 0 | 0 | 8 | 3 | 7 | 0 | 17 | 3 | 12 | 3 | 15 | 3 | 6
EXPORTS | 1 | 3 | 17
IMPORTS | 1 | 3 | 15
EQ | 23 | 
    "rbuf<0>".T  =  ;Imported pterms FB4_16
	  /rst * "rxcnt16<0>" * "rxcnt16<1>" * 
	"rxcnt16<2>" * "rxcnt16<3>" * "rxd_cnt<0>.FBK".LFBK * 
	"rxd_cnt<3>.FBK".LFBK * "rxd_shift<0>.FBK".LFBK * /"rxd_cnt<1>.FBK".LFBK * 
	/"rxd_cnt<2>.FBK".LFBK * /"N_rbuf<0>.FBK".LFBK
	+ /rst * "rxcnt16<0>" * "rxcnt16<1>" * 
	"rxcnt16<2>" * "rxcnt16<3>" * "rxd_cnt<0>.FBK".LFBK * 
	"rxd_cnt<3>.FBK".LFBK * /"rxd_shift<0>.FBK".LFBK * /"rxd_cnt<1>.FBK".LFBK * 
	/"rxd_cnt<2>.FBK".LFBK * "N_rbuf<0>.FBK".LFBK
    "rbuf<0>".CLKF  =  N_bclk.FBK.LFBK
    "rbuf<0>".PRLD  =  GND
    N_rbuf<0>.EXP  =  "txd_cnt<0>" * "txcnt16<1>" * "txcnt16<0>" * 
	"txcnt16<2>" * "txcnt16<3>" * /"txd_shift<1>" * 
	"txd_cnt<3>.FBK".LFBK * "txd_shift<0>.FBK".LFBK
	+ "txcnt16<1>" * "txcnt16<0>" * "txcnt16<2>" * 
	"txcnt16<3>" * "txd_shift<1>" * "txd_cnt<1>.FBK".LFBK * 
	/"txd_cnt<3>.FBK".LFBK * /"txd_shift<0>.FBK".LFBK
	+ "txcnt16<1>" * "txcnt16<0>" * "txcnt16<2>" * 
	"txcnt16<3>" * "txd_shift<1>" * /"txd_cnt<1>.FBK".LFBK * 
	"txd_cnt<3>.FBK".LFBK * /"txd_shift<0>.FBK".LFBK
	+ "txcnt16<1>" * "txcnt16<0>" * "txcnt16<2>" * 
	"txcnt16<3>" * /"txd_shift<1>" * /"txd_cnt<1>.FBK".LFBK * 
	"txd_cnt<3>.FBK".LFBK * "txd_shift<0>.FBK".LFBK

MACROCELL | 1 | 1 | N_rbuf<1>
ATTRIBUTES | 4653858 | 0
OUTPUTMC | 2 | 1 | 0 | 1 | 1
INPUTS | 10 | rst  | rxd_cnt<0>  | FC_1_.OUT  | rxcnt16<0>.FBK".LFBK  | rxd_shift<1>.FBK".LFBK  | N_rec_ready.FBK.LFBK  | N_rbuf<1>.FBK".LFBK  | bclk.PIN  | rxd_cnt<3>  | FC_0_.OUT
INPUTMC | 6 | 3 | 10 | 1 | 11 | 1 | 2 | 1 | 0 | 1 | 1 | 3 | 9
INPUTP | 2 | 32 | 77
EXPORTS | 1 | 1 | 0
EQ | 12 | 
    "rbuf<1>".T  =  /rst * "rxd_cnt<0>" * "rxd_cnt<3>" * FC_0_.OUT * 
	FC_1_.OUT * "rxcnt16<0>.FBK".LFBK * "rxd_shift<1>.FBK".LFBK * 
	/"N_rbuf<1>.FBK".LFBK
	+ /rst * "rxd_cnt<0>" * "rxd_cnt<3>" * FC_0_.OUT * 
	FC_1_.OUT * "rxcnt16<0>.FBK".LFBK * /"rxd_shift<1>.FBK".LFBK * 
	"N_rbuf<1>.FBK".LFBK
    "rbuf<1>".CLKF  =  bclk.PIN
    "rbuf<1>".PRLD  =  GND
    N_rbuf<1>.EXP  =  /"rxd_cnt<0>" * "rxd_cnt<3>" * FC_1_.OUT * 
	N_rec_ready.FBK.LFBK * "rxcnt16<0>.FBK".LFBK
	+ "rxd_cnt<0>" * "rxd_cnt<3>" * FC_0_.OUT * 
	FC_1_.OUT * /N_rec_ready.FBK.LFBK * "rxcnt16<0>.FBK".LFBK

MACROCELL | 1 | 3 | N_rbuf<2>
ATTRIBUTES | 4653858 | 0
OUTPUTMC | 3 | 1 | 2 | 1 | 3 | 1 | 4
INPUTS | 11 | rst  | rxd_cnt<0>  | FC_1_.OUT  | rxcnt16<0>.FBK".LFBK  | rxd_shift<2>.FBK".LFBK  | N_rbuf<4>.EXP  | rxd_shift<1>.FBK".LFBK  | N_rbuf<2>.FBK".LFBK  | rxd_cnt<3>  | bclk.PIN  | FC_0_.OUT
INPUTMC | 7 | 3 | 10 | 1 | 11 | 1 | 17 | 1 | 4 | 1 | 2 | 1 | 3 | 3 | 9
INPUTP | 2 | 32 | 77
EXPORTS | 1 | 1 | 2
IMPORTS | 1 | 1 | 4
EQ | 15 | 
    "rbuf<2>".T  =  /rst * "rxd_cnt<0>" * "rxd_cnt<3>" * FC_0_.OUT * 
	FC_1_.OUT * "rxcnt16<0>.FBK".LFBK * "rxd_shift<2>.FBK".LFBK * 
	/"N_rbuf<2>.FBK".LFBK
;Imported pterms FB2_5
	+ /rst * "rxd_cnt<0>" * "rxd_cnt<3>" * FC_0_.OUT * 
	FC_1_.OUT * "rxcnt16<0>.FBK".LFBK * /"rxd_shift<2>.FBK".LFBK * 
	"N_rbuf<2>.FBK".LFBK
    "rbuf<2>".CLKF  =  bclk.PIN
    "rbuf<2>".PRLD  =  GND
    N_rbuf<2>.EXP  =  "rxd_cnt<0>" * /"rxd_cnt<3>" * FC_1_.OUT * 
	"rxcnt16<0>.FBK".LFBK * "rxd_shift<2>.FBK".LFBK * /"rxd_shift<1>.FBK".LFBK
	+ /"rxd_cnt<0>" * "rxd_cnt<3>" * FC_1_.OUT * 
	"rxcnt16<0>.FBK".LFBK * "rxd_shift<2>.FBK".LFBK * /"rxd_shift<1>.FBK".LFBK
	+ /"rxd_cnt<0>" * "rxd_cnt<3>" * FC_1_.OUT * 
	"rxcnt16<0>.FBK".LFBK * /"rxd_shift<2>.FBK".LFBK * "rxd_shift<1>.FBK".LFBK

MACROCELL | 1 | 5 | N_rbuf<3>
ATTRIBUTES | 4653858 | 0
OUTPUTMC | 1 | 1 | 5
INPUTS | 9 | rst  | rxd_cnt<0>  | FC_1_.OUT  | rxcnt16<0>.FBK".LFBK  | rxd_shift<3>.FBK".LFBK  | N_rbuf<3>.FBK".LFBK  | bclk.PIN  | rxd_cnt<3>  | FC_0_.OUT
INPUTMC | 5 | 3 | 10 | 1 | 11 | 1 | 16 | 1 | 5 | 3 | 9
INPUTP | 2 | 32 | 77
EQ | 8 | 
    "rbuf<3>".T  =  /rst * "rxd_cnt<0>" * "rxd_cnt<3>" * FC_0_.OUT * 
	FC_1_.OUT * "rxcnt16<0>.FBK".LFBK * "rxd_shift<3>.FBK".LFBK * 
	/"N_rbuf<3>.FBK".LFBK
	+ /rst * "rxd_cnt<0>" * "rxd_cnt<3>" * FC_0_.OUT * 
	FC_1_.OUT * "rxcnt16<0>.FBK".LFBK * /"rxd_shift<3>.FBK".LFBK * 
	"N_rbuf<3>.FBK".LFBK
    "rbuf<3>".CLKF  =  bclk.PIN
    "rbuf<3>".PRLD  =  GND

MACROCELL | 1 | 4 | N_rbuf<4>
ATTRIBUTES | 4653858 | 0
OUTPUTMC | 2 | 1 | 3 | 1 | 4
INPUTS | 11 | rst  | rxd_cnt<0>  | FC_1_.OUT  | rxcnt16<0>.FBK".LFBK  | N_rbuf<2>.FBK".LFBK  | rxd_shift<4>.FBK".LFBK  | rxd_shift<2>.FBK".LFBK  | N_rbuf<4>.FBK".LFBK  | rxd_cnt<3>  | bclk.PIN  | FC_0_.OUT
INPUTMC | 7 | 3 | 10 | 1 | 11 | 1 | 3 | 1
ex25.mfd - 源码说明

本页面展示了「[VHDL经典设计26例]--在xilinx芯片上调试通过--[01--1位全加器][02--2选1多路选择器][03--8位硬件加法器][04--7段数码显示译码器][05--8位串入并出寄存器][」中的 ex25.mfd 源码文件，采用 MFD 编程语言编写，共 1,250 行代码。您可以在线阅读完整代码内容，也可以返回资源详情页下载完整源码包进行本地学习和开发。
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