ex25.mfd

来自「[VHDL经典设计26例]--在xilinx芯片上调试通过--[01--1位全加」· MFD 代码 · 共 1,250 行 · 第 1/5 页
MFD
1,250 行
    "rxd_shift<1>".PRLD  =  GND

MACROCELL | 1 | 17 | rxd_shift<2>
ATTRIBUTES | 4391728 | 0
OUTPUTMC | 6 | 1 | 0 | 1 | 2 | 1 | 17 | 1 | 16 | 1 | 3 | 1 | 4
INPUTS | 11 | FC_1_.OUT  | rxd_shift<2>.FBK".LFBK  | N_rec_ready.EXP  | rxd_shift<3>.EXP  | rxcnt16<0>.FBK".LFBK  | rxd_shift<3>.FBK".LFBK  | bclk.PIN  | rxd_cnt<0>  | rxd_cnt<3>  | rst  | FC_0_.OUT
INPUTMC | 7 | 1 | 17 | 1 | 0 | 1 | 16 | 1 | 11 | 1 | 16 | 3 | 10 | 3 | 9
INPUTP | 2 | 77 | 32
IMPORTS | 2 | 1 | 0 | 1 | 16
EQ | 17 | 
    "rxd_shift<2>".T  =  /FC_0_.OUT * FC_1_.OUT * "rxcnt16<0>.FBK".LFBK * 
	"rxd_shift<2>.FBK".LFBK * /"rxd_shift<3>.FBK".LFBK
	+ /FC_0_.OUT * FC_1_.OUT * "rxcnt16<0>.FBK".LFBK * 
	/"rxd_shift<2>.FBK".LFBK * "rxd_shift<3>.FBK".LFBK
	+ "rxd_cnt<0>" * /"rxd_cnt<3>" * FC_1_.OUT * 
	"rxcnt16<0>.FBK".LFBK * "rxd_shift<2>.FBK".LFBK * /"rxd_shift<3>.FBK".LFBK
;Imported pterms FB2_1
	+ /"rxd_cnt<0>" * "rxd_cnt<3>" * FC_1_.OUT * 
	"rxcnt16<0>.FBK".LFBK * /"rxd_shift<2>.FBK".LFBK * "rxd_shift<3>.FBK".LFBK
;Imported pterms FB2_17
	+ "rxd_cnt<0>" * /"rxd_cnt<3>" * FC_1_.OUT * 
	"rxcnt16<0>.FBK".LFBK * /"rxd_shift<2>.FBK".LFBK * "rxd_shift<3>.FBK".LFBK
	+ /"rxd_cnt<0>" * "rxd_cnt<3>" * FC_1_.OUT * 
	"rxcnt16<0>.FBK".LFBK * "rxd_shift<2>.FBK".LFBK * /"rxd_shift<3>.FBK".LFBK
    "rxd_shift<2>".CLKF  =  bclk.PIN
    "rxd_shift<2>".RSTF  =  rst
    "rxd_shift<2>".PRLD  =  GND

MACROCELL | 1 | 16 | rxd_shift<3>
ATTRIBUTES | 4391728 | 0
OUTPUTMC | 5 | 1 | 17 | 1 | 0 | 1 | 16 | 1 | 5 | 1 | 15
INPUTS | 11 | FC_1_.OUT  | rxd_shift<2>.FBK".LFBK  | rxd_cnt<0>  | rxd_cnt<3>  | rxd_shift<3>.FBK".LFBK  | rxd_shift<4>.FBK".LFBK  | bclk.PIN  | EXP9_.EXP  | rxcnt16<0>.FBK".LFBK  | rst  | FC_0_.OUT
INPUTMC | 7 | 1 | 17 | 3 | 10 | 3 | 9 | 1 | 16 | 1 | 12 | 1 | 15 | 1 | 11
INPUTP | 2 | 77 | 32
EXPORTS | 1 | 1 | 17
IMPORTS | 1 | 1 | 15
EQ | 20 | 
    "rxd_shift<3>".T  =  /FC_0_.OUT * FC_1_.OUT * "rxcnt16<0>.FBK".LFBK * 
	"rxd_shift<3>.FBK".LFBK * /"rxd_shift<4>.FBK".LFBK
;Imported pterms FB2_16
	+ /FC_0_.OUT * FC_1_.OUT * "rxcnt16<0>.FBK".LFBK * 
	/"rxd_shift<3>.FBK".LFBK * "rxd_shift<4>.FBK".LFBK
	+ "rxd_cnt<0>" * /"rxd_cnt<3>" * FC_1_.OUT * 
	"rxcnt16<0>.FBK".LFBK * "rxd_shift<3>.FBK".LFBK * /"rxd_shift<4>.FBK".LFBK
	+ "rxd_cnt<0>" * /"rxd_cnt<3>" * FC_1_.OUT * 
	"rxcnt16<0>.FBK".LFBK * /"rxd_shift<3>.FBK".LFBK * "rxd_shift<4>.FBK".LFBK
	+ /"rxd_cnt<0>" * "rxd_cnt<3>" * FC_1_.OUT * 
	"rxcnt16<0>.FBK".LFBK * "rxd_shift<3>.FBK".LFBK * /"rxd_shift<4>.FBK".LFBK
	+ /"rxd_cnt<0>" * "rxd_cnt<3>" * FC_1_.OUT * 
	"rxcnt16<0>.FBK".LFBK * /"rxd_shift<3>.FBK".LFBK * "rxd_shift<4>.FBK".LFBK
    "rxd_shift<3>".CLKF  =  bclk.PIN
    "rxd_shift<3>".RSTF  =  rst
    "rxd_shift<3>".PRLD  =  GND
    rxd_shift<3>.EXP  =  "rxd_cnt<0>" * /"rxd_cnt<3>" * FC_1_.OUT * 
	"rxcnt16<0>.FBK".LFBK * /"rxd_shift<2>.FBK".LFBK * "rxd_shift<3>.FBK".LFBK
	+ /"rxd_cnt<0>" * "rxd_cnt<3>" * FC_1_.OUT * 
	"rxcnt16<0>.FBK".LFBK * "rxd_shift<2>.FBK".LFBK * /"rxd_shift<3>.FBK".LFBK

MACROCELL | 1 | 12 | rxd_shift<4>
ATTRIBUTES | 4391728 | 0
OUTPUTMC | 6 | 1 | 11 | 1 | 16 | 1 | 12 | 1 | 13 | 1 | 4 | 1 | 15
INPUTS | 11 | FC_1_.OUT  | rxd_shift<4>.FBK".LFBK  | rxcnt16<0>.EXP  | rxd_shift<5>.EXP  | rxcnt16<0>.FBK".LFBK  | rxd_shift<5>.FBK".LFBK  | bclk.PIN  | rxd_cnt<0>  | rxd_cnt<3>  | rst  | FC_0_.OUT
INPUTMC | 7 | 1 | 12 | 1 | 11 | 1 | 13 | 1 | 11 | 1 | 13 | 3 | 10 | 3 | 9
INPUTP | 2 | 77 | 32
IMPORTS | 2 | 1 | 11 | 1 | 13
EQ | 17 | 
    "rxd_shift<4>".T  =  /FC_0_.OUT * FC_1_.OUT * "rxcnt16<0>.FBK".LFBK * 
	"rxd_shift<4>.FBK".LFBK * /"rxd_shift<5>.FBK".LFBK
	+ /FC_0_.OUT * FC_1_.OUT * "rxcnt16<0>.FBK".LFBK * 
	/"rxd_shift<4>.FBK".LFBK * "rxd_shift<5>.FBK".LFBK
	+ "rxd_cnt<0>" * /"rxd_cnt<3>" * FC_1_.OUT * 
	"rxcnt16<0>.FBK".LFBK * "rxd_shift<4>.FBK".LFBK * /"rxd_shift<5>.FBK".LFBK
;Imported pterms FB2_12
	+ "rxd_cnt<0>" * /"rxd_cnt<3>" * FC_1_.OUT * 
	"rxcnt16<0>.FBK".LFBK * /"rxd_shift<4>.FBK".LFBK * "rxd_shift<5>.FBK".LFBK
	+ /"rxd_cnt<0>" * "rxd_cnt<3>" * FC_1_.OUT * 
	"rxcnt16<0>.FBK".LFBK * "rxd_shift<4>.FBK".LFBK * /"rxd_shift<5>.FBK".LFBK
;Imported pterms FB2_14
	+ /"rxd_cnt<0>" * "rxd_cnt<3>" * FC_1_.OUT * 
	"rxcnt16<0>.FBK".LFBK * /"rxd_shift<4>.FBK".LFBK * "rxd_shift<5>.FBK".LFBK
    "rxd_shift<4>".CLKF  =  bclk.PIN
    "rxd_shift<4>".RSTF  =  rst
    "rxd_shift<4>".PRLD  =  GND

MACROCELL | 1 | 13 | rxd_shift<5>
ATTRIBUTES | 4391728 | 0
OUTPUTMC | 5 | 1 | 12 | 1 | 11 | 1 | 13 | 1 | 6 | 1 | 14
INPUTS | 11 | FC_1_.OUT  | rxd_shift<4>.FBK".LFBK  | rxd_cnt<0>  | rxd_cnt<3>  | rxd_shift<5>.FBK".LFBK  | rxd_shift<6>.FBK".LFBK  | bclk.PIN  | EXP8_.EXP  | rxcnt16<0>.FBK".LFBK  | rst  | FC_0_.OUT
INPUTMC | 7 | 1 | 12 | 3 | 10 | 3 | 9 | 1 | 13 | 1 | 9 | 1 | 14 | 1 | 11
INPUTP | 2 | 77 | 32
EXPORTS | 1 | 1 | 12
IMPORTS | 1 | 1 | 14
EQ | 18 | 
    "rxd_shift<5>".T  =  /FC_0_.OUT * FC_1_.OUT * "rxcnt16<0>.FBK".LFBK * 
	"rxd_shift<5>.FBK".LFBK * /"rxd_shift<6>.FBK".LFBK
	+ /FC_0_.OUT * FC_1_.OUT * "rxcnt16<0>.FBK".LFBK * 
	/"rxd_shift<5>.FBK".LFBK * "rxd_shift<6>.FBK".LFBK
;Imported pterms FB2_15
	+ "rxd_cnt<0>" * /"rxd_cnt<3>" * FC_1_.OUT * 
	"rxcnt16<0>.FBK".LFBK * "rxd_shift<5>.FBK".LFBK * /"rxd_shift<6>.FBK".LFBK
	+ "rxd_cnt<0>" * /"rxd_cnt<3>" * FC_1_.OUT * 
	"rxcnt16<0>.FBK".LFBK * /"rxd_shift<5>.FBK".LFBK * "rxd_shift<6>.FBK".LFBK
	+ /"rxd_cnt<0>" * "rxd_cnt<3>" * FC_1_.OUT * 
	"rxcnt16<0>.FBK".LFBK * "rxd_shift<5>.FBK".LFBK * /"rxd_shift<6>.FBK".LFBK
	+ /"rxd_cnt<0>" * "rxd_cnt<3>" * FC_1_.OUT * 
	"rxcnt16<0>.FBK".LFBK * /"rxd_shift<5>.FBK".LFBK * "rxd_shift<6>.FBK".LFBK
    "rxd_shift<5>".CLKF  =  bclk.PIN
    "rxd_shift<5>".RSTF  =  rst
    "rxd_shift<5>".PRLD  =  GND
    rxd_shift<5>.EXP  =  /"rxd_cnt<0>" * "rxd_cnt<3>" * FC_1_.OUT * 
	"rxcnt16<0>.FBK".LFBK * /"rxd_shift<4>.FBK".LFBK * "rxd_shift<5>.FBK".LFBK

MACROCELL | 1 | 9 | rxd_shift<6>
ATTRIBUTES | 4391728 | 0
OUTPUTMC | 6 | 1 | 13 | 1 | 9 | 1 | 8 | 1 | 6 | 1 | 10 | 1 | 14
INPUTS | 11 | FC_1_.OUT  | rxd_shift<6>.FBK".LFBK  | rxd_shift<7>.EXP  | N_rbuf<7>.EXP  | rxcnt16<0>.FBK".LFBK  | rxd_shift<7>.FBK".LFBK  | bclk.PIN  | rxd_cnt<0>  | rxd_cnt<3>  | rst  | FC_0_.OUT
INPUTMC | 7 | 1 | 9 | 1 | 8 | 1 | 10 | 1 | 11 | 1 | 8 | 3 | 10 | 3 | 9
INPUTP | 2 | 77 | 32
IMPORTS | 2 | 1 | 8 | 1 | 10
EQ | 17 | 
    "rxd_shift<6>".T  =  /FC_0_.OUT * FC_1_.OUT * "rxcnt16<0>.FBK".LFBK * 
	"rxd_shift<6>.FBK".LFBK * /"rxd_shift<7>.FBK".LFBK
	+ /FC_0_.OUT * FC_1_.OUT * "rxcnt16<0>.FBK".LFBK * 
	/"rxd_shift<6>.FBK".LFBK * "rxd_shift<7>.FBK".LFBK
	+ "rxd_cnt<0>" * /"rxd_cnt<3>" * FC_1_.OUT * 
	"rxcnt16<0>.FBK".LFBK * "rxd_shift<6>.FBK".LFBK * /"rxd_shift<7>.FBK".LFBK
;Imported pterms FB2_9
	+ "rxd_cnt<0>" * /"rxd_cnt<3>" * FC_1_.OUT * 
	"rxcnt16<0>.FBK".LFBK * /"rxd_shift<6>.FBK".LFBK * "rxd_shift<7>.FBK".LFBK
;Imported pterms FB2_11
	+ /"rxd_cnt<0>" * "rxd_cnt<3>" * FC_1_.OUT * 
	"rxcnt16<0>.FBK".LFBK * "rxd_shift<6>.FBK".LFBK * /"rxd_shift<7>.FBK".LFBK
	+ /"rxd_cnt<0>" * "rxd_cnt<3>" * FC_1_.OUT * 
	"rxcnt16<0>.FBK".LFBK * /"rxd_shift<6>.FBK".LFBK * "rxd_shift<7>.FBK".LFBK
    "rxd_shift<6>".CLKF  =  bclk.PIN
    "rxd_shift<6>".RSTF  =  rst
    "rxd_shift<6>".PRLD  =  GND

MACROCELL | 1 | 8 | rxd_shift<7>
ATTRIBUTES | 4391728 | 0
OUTPUTMC | 4 | 1 | 9 | 1 | 8 | 1 | 7 | 1 | 10
INPUTS | 11 | FC_1_.OUT  | rxd_shift<6>.FBK".LFBK  | rxd_cnt<0>  | rxd_cnt<3>  | rxd_shift<7>.FBK".LFBK  | bclk.PIN  | rxd_sync  | N_rbuf<5>.EXP  | rxcnt16<0>.FBK".LFBK  | rst  | FC_0_.OUT
INPUTMC | 7 | 1 | 9 | 3 | 10 | 3 | 9 | 1 | 8 | 2 | 14 | 1 | 7 | 1 | 11
INPUTP | 2 | 77 | 32
EXPORTS | 1 | 1 | 9
IMPORTS | 1 | 1 | 7
EQ | 18 | 
    "rxd_shift<7>".T  =  rxd_sync * /FC_0_.OUT * FC_1_.OUT * 
	"rxcnt16<0>.FBK".LFBK * /"rxd_shift<7>.FBK".LFBK
	+ /rxd_sync * /FC_0_.OUT * FC_1_.OUT * 
	"rxcnt16<0>.FBK".LFBK * "rxd_shift<7>.FBK".LFBK
;Imported pterms FB2_8
	+ "rxd_cnt<0>" * /"rxd_cnt<3>" * rxd_sync * 
	FC_1_.OUT * "rxcnt16<0>.FBK".LFBK * /"rxd_shift<7>.FBK".LFBK
	+ "rxd_cnt<0>" * /"rxd_cnt<3>" * /rxd_sync * 
	FC_1_.OUT * "rxcnt16<0>.FBK".LFBK * "rxd_shift<7>.FBK".LFBK
	+ /"rxd_cnt<0>" * "rxd_cnt<3>" * rxd_sync * 
	FC_1_.OUT * "rxcnt16<0>.FBK".LFBK * /"rxd_shift<7>.FBK".LFBK
	+ /"rxd_cnt<0>" * "rxd_cnt<3>" * /rxd_sync * 
	FC_1_.OUT * "rxcnt16<0>.FBK".LFBK * "rxd_shift<7>.FBK".LFBK
    "rxd_shift<7>".CLKF  =  bclk.PIN
    "rxd_shift<7>".RSTF  =  rst
    "rxd_shift<7>".PRLD  =  GND
    rxd_shift<7>.EXP  =  "rxd_cnt<0>" * /"rxd_cnt<3>" * FC_1_.OUT * 
	"rxcnt16<0>.FBK".LFBK * /"rxd_shift<6>.FBK".LFBK * "rxd_shift<7>.FBK".LFBK

MACROCELL | 2 | 14 | rxd_sync
ATTRIBUTES | 4391840 | 0
OUTPUTMC | 6 | 1 | 11 | 1 | 7 | 1 | 8 | 2 | 15 | 2 | 0 | 2 | 14
INPUTS | 9 | samples<0>.FBK".LFBK  | rxd  | bclk.PIN  | rst  | rxd_cnt<0>  | rxd_cnt<1>  | rxd_cnt<2>  | rxd_cnt<3>  | rxd_sync.FBK.LFBK
INPUTMC | 6 | 2 | 13 | 3 | 10 | 3 | 8 | 3 | 2 | 3 | 9 | 2 | 14
INPUTP | 3 | 71 | 77 | 32
EXPORTS | 1 | 2 | 15
EQ | 7 | 
    rxd_sync.T  =  rxd * /rxd_sync.FBK.LFBK * "samples<0>.FBK".LFBK
	+ /rxd * rxd_sync.FBK.LFBK * /"samples<0>.FBK".LFBK
    rxd_sync.CLKF  =  bclk.PIN
    rxd_sync.SETF  =  rst
    rxd_sync.PRLD  =  GND
    rxd_sync.EXP  =  /"rxd_cnt<0>" * /"rxd_cnt<1>" * /"rxd_cnt<2>" * 
	/"rxd_cnt<3>" * rxd_sync.FBK.LFBK

MACROCELL | 2 | 12 | txcnt16<0>
ATTRIBUTES | 8586032 | 0
OUTPUTMC | 30 | 3 | 15 | 3 | 3 | 0 | 1 | 3 | 7 | 3 | 1 | 3 | 6 | 3 | 16 | 3 | 4 | 0 | 0 | 0 | 8 | 3 | 17 | 0 | 17 | 0 | 14 | 0 | 13 | 0 | 9 | 0 | 6 | 0 | 4 | 0 | 7 | 0 | 2 | 0 | 3 | 0 | 5 | 0 | 10 | 0 | 11 | 0 | 12 | 0 | 15 | 0 | 16 | 3 | 0 | 3 | 2 | 2 | 11 | 2 | 12
INPUTS | 3 | bclk.PIN  | rst  | txcnt16<0>.FBK".LFBK
INPUTMC | 1 | 2 | 12
INPUTP | 2 | 77 | 32
EQ | 4 | 
    "txcnt16<0>"  :=  /"txcnt16<0>.FBK".LFBK
    "txcnt16<0>".CLKF  =  bclk.PIN
    "txcnt16<0>".RSTF  =  rst
    "txcnt16<0>".PRLD  =  GND

MACROCELL | 0 | 0 | txcnt16<2>
ATTRIBUTES | 4391728 | 0
OUTPUTMC | 27 | 3 | 15 | 3 | 3 | 3 | 16 | 3 | 7 | 3 | 1 | 3 | 6 | 3 | 0 | 3 | 17 | 3 | 4 | 0 | 17 | 0 | 2 | 0 | 0 | 0 | 8 | 0 | 14 | 0 | 13 | 0 | 9 | 0 | 6 | 0 | 4 | 0 | 7 | 0 | 1 | 0 | 3 | 0 | 5 | 0 | 10 | 0 | 11 | 0 | 12 | 0 | 15 | 0 | 16
INPUTS | 12 | txcnt16<1>  | txcnt16<0>  | rst  | txcnt16<2>.FBK".LFBK  | txd_cnt<1>  | txd_cnt<2>  | txd_cnt<3>  | txcnt16<3>.FBK".LFBK  | txd_shift<1>.FBK".LFBK  | bclk.PIN  | tbuf<1>  | txd_cnt<0>.FBK".LFBK
INPUTMC | 9 | 2 | 11 | 2 | 12 | 0 | 0 | 3 | 7 | 3 | 1 | 3 | 6 | 0 | 8 | 0 | 17 | 0 | 2
INPUTP | 3 | 32 | 77 | 46
EXPORTS | 1 | 0 | 17
EQ | 10 | 
    "txcnt16<2>".T  =  "txcnt16<1>" * "txcnt16<0>"
    "txcnt16<2>".CLKF  =  bclk.PIN
    "txcnt16<2>".RSTF  =  rst
    "txcnt16<2>".PRLD  =  GND
    txcnt16<2>.EXP  =  /"txd_cnt<1>" * /"txd_cnt<2>" * /"txd_cnt<3>" * 
	"txcnt16<1>" * "txcnt16<0>" * "tbuf<1>" * "txd_cnt<0>.FBK".LFBK * 
	"txcnt16<2>.FBK".LFBK * "txcnt16<3>.FBK".LFBK * /"txd_shift<1>.FBK".LFBK
	+ /"txd_cnt<1>" * /"txd_cnt<2>" * /"txd_cnt<3>" * 
	"txcnt16<1>" * "txcnt16<0>" * /"tbuf<1>" * "txd_cnt<0>.FBK".LFBK * 
	"txcnt16<2>.FBK".LFBK * "txcnt16<3>.FBK".LFBK * "txd_shift<1>.FBK".LFBK

MACROCELL | 0 | 8 | txcnt16<3>
ATTRIBUTES | 4391728 | 0
OUTPUTMC | 28 | 3 | 15 | 3 | 3 | 3 | 16 | 3 | 7 | 3 | 1 | 3 | 6 | 3 | 17 | 3 | 0 | 3 | 4 | 3 | 2 | 0 | 9 | 0 | 2 | 0 | 0 | 0 | 8 | 0 | 17 | 0 | 14 | 0 | 13 | 0 | 6 | 0 | 4 | 0 | 7 | 0 | 1 | 0 | 3 | 0 | 5 | 0 | 10 | 0 | 11 | 0 | 12 | 0 | 15 | 0 | 16
INPUTS | 11 | txcnt16<1>  | txcnt16<0>  | txd_cnt<0>.FBK".LFBK  | rst  | txcnt16<3>.FBK".LFBK  | txd_cnt<3>  | txd_shift<4>.FBK".LFBK  | txd_shift<5>.FBK".LFBK  | bclk.PIN  | txd_cnt<1>  | txcnt16<2>.FBK".LFBK
INPUTMC | 9 | 2 | 11 | 2 | 12 | 0 | 2 | 0 | 8 | 3 | 6 | 0 | 9 | 0 | 6 | 3 | 7 | 0 | 0
INPUTP | 2 | 32 | 77
EXPORTS | 1 | 0 | 9
EQ | 11 | 
    "txcnt16<3>".T  =  "txcnt16<1>" * "txcnt16<0>" * 
	"txcnt16<2>.FBK".LFBK
    "txcnt16<3>".CLKF  =  bclk.PIN
    "txcnt16<3>".RSTF  =  rst
    "txcnt16<3>".PRLD  =  GND
    txcnt16<3>.EXP  =  /"txd_cnt<1>" * "txd_cnt<3>" * "txcnt16<1>" * 
	"txcnt16<0>" * "txcnt16<2>.FBK".LFBK * "txcnt16<3>.FBK".LFBK * 
	"txd_shift<4>.FBK".LFBK * /"txd_shift<5>.FBK".LFBK
	+ "txd_cnt<3>" * "txcnt16<1>" * "txcnt16<0>" * 
	"txd_cnt<0>.FBK".LFBK * "txcnt16<2>.FBK".LFBK * "txcnt16<3>.FBK".LFBK * 
	"txd_shift<4>.FBK".LFBK * /"txd_shift<5>.FBK".LFBK

MACROCELL | 3 | 0 | baud_cnt<4>
ATTRIBUTES | 4424464 | 0
OUTPUTMC | 4 | 3 | 17 | 3 | 5 | 3 | 0 | 3 | 13
INPUTS | 18 | baud_cnt<3>.FBK".LFBK  | baud_cnt<0>  | baud_cnt<2>  | baud_cnt<4>.FBK".LFBK  | txd_cnt<3>.FBK".LFBK  | rst  | txd_cnt<0>  | txd_shift<0>.FBK".LFBK  | txcnt16<1>  | txcnt16<0>  | txcnt16<2>  | txcnt16<3>  | txd_cnt<1>.FBK".LFBK  | txd_shift<1>  | txd_cnt<2>.FBK".LFBK  | tbuf<0>  | txd_cnt<2>.EXP  | baud_cnt<1>.FBK".LFBK
INPUTMC | 16 | 3 | 4 | 2 | 10 | 2 | 0 | 3 | 0 | 3 | 6 | 0 | 2 | 3 | 17 | 2 | 11 | 2 | 12 | 0 | 0 | 0 | 8 | 3 | 7 | 0 | 17 | 3 | 1 | 3 | 1 | 3 | 5
INPUTP | 2 | 32 | 49
EXPORTS | 1 | 3 | 17
IMPORTS | 1 | 3 | 1
EQ | 17 | 
    "baud_cnt<4>".T  =  "baud_cnt<0>" * /"baud_cnt<2>" * 
	/"baud_cnt<1>.FBK".LFBK * "baud_cnt<3>.FBK".LFBK * "baud_cnt<4>.FBK".LFBK
;Imported pterms FB4_2
	+ "baud_cnt<0>" * "baud_cnt<2>" * 
	"baud_cnt<1>.FBK".LFBK * "baud_cnt<3>.FBK".LFBK
    "baud_cnt<4>".CLKF  =  clk	;FCLK/GCK
    "baud_cnt<4>".RSTF  =  rst
    "baud_cnt<4>".PRLD  =  GND
ex25.mfd - 源码说明

本页面展示了「[VHDL经典设计26例]--在xilinx芯片上调试通过--[01--1位全加器][02--2选1多路选择器][03--8位硬件加法器][04--7段数码显示译码器][05--8位串入并出寄存器][」中的 ex25.mfd 源码文件，采用 MFD 编程语言编写，共 1,250 行代码。您可以在线阅读完整代码内容，也可以返回资源详情页下载完整源码包进行本地学习和开发。
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