ex25.mod

来自「[VHDL经典设计26例]--在xilinx芯片上调试通过--[01--1位全加」· MOD 代码 · 共 48 行

MODEL
MODEL_VERSION "v1998.8";
DESIGN "ex25";

/* port names and type */
INPUT S:PIN10 = clk;
INPUT S:PIN20 = rst;
INPUT S:PIN23 = xmit_cmd;
INPUT S:PIN56 = rxd;
INPUT S:PIN36 = tbuf<0>;
INPUT S:PIN33 = tbuf<1>;
INPUT S:PIN35 = tbuf<2>;
INPUT S:PIN37 = tbuf<3>;
INPUT S:PIN40 = tbuf<4>;
INPUT S:PIN39 = tbuf<5>;
INPUT S:PIN41 = tbuf<6>;
INPUT S:PIN43 = tbuf<7>;
OUTPUT S:PIN61 = bclk;
OUTPUT S:PIN62 = xmit_done;
OUTPUT S:PIN63 = rec_ready;
OUTPUT S:PIN52 = txd;
OUTPUT S:PIN66 = rbuf<0>;
OUTPUT S:PIN69 = rbuf<1>;
OUTPUT S:PIN68 = rbuf<2>;
OUTPUT S:PIN71 = rbuf<3>;
OUTPUT S:PIN70 = rbuf<4>;
OUTPUT S:PIN72 = rbuf<5>;
OUTPUT S:PIN76 = rbuf<6>;
OUTPUT S:PIN77 = rbuf<7>;

/* timing arc definitions */
clk_bclk_delay: DELAY clk bclk;
clk_xmit_done_delay: DELAY clk xmit_done;
clk_rec_ready_delay: DELAY clk rec_ready;
clk_txd_delay: DELAY clk txd;
clk_rbuf<0>_delay: DELAY clk rbuf<0>;
clk_rbuf<1>_delay: DELAY clk rbuf<1>;
clk_rbuf<2>_delay: DELAY clk rbuf<2>;
clk_rbuf<3>_delay: DELAY clk rbuf<3>;
clk_rbuf<4>_delay: DELAY clk rbuf<4>;
clk_rbuf<5>_delay: DELAY clk rbuf<5>;
clk_rbuf<6>_delay: DELAY clk rbuf<6>;
clk_rbuf<7>_delay: DELAY clk rbuf<7>;

/* timing check arc definitions */

ENDMODEL