ex25.rpt

来自「[VHDL经典设计26例]--在xilinx芯片上调试通过--[01--1位全加」· RPT 代码 · 共 1,248 行 · 第 1/5 页

RPT
1,248 行
字号
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	"txcnt16<1>" * "txcnt16<0>" * "tbuf<2>" * "txd_cnt<0>.FBK".LFBK * 
	"txcnt16<2>.FBK".LFBK * "txcnt16<3>.FBK".LFBK * /"txd_shift<2>.FBK".LFBK
	+ /"txd_cnt<1>" * /"txd_cnt<2>" * /"txd_cnt<3>" * 
	"txcnt16<1>" * "txcnt16<0>" * /"tbuf<2>" * "txd_cnt<0>.FBK".LFBK * 
	"txcnt16<2>.FBK".LFBK * "txcnt16<3>.FBK".LFBK * "txd_shift<2>.FBK".LFBK
    "txd_shift<2>".CLKF  =  bclk.PIN
    "txd_shift<2>".RSTF  =  rst
    "txd_shift<2>".PRLD  =  GND    

 "txd_shift<3>".T  =  "txd_cnt<2>" * "txcnt16<1>" * "txcnt16<0>" * 
	"txcnt16<2>.FBK".LFBK * "txcnt16<3>.FBK".LFBK * /"txd_shift<4>.FBK".LFBK * 
	"txd_shift<3>.FBK".LFBK
;Imported pterms FB1_13
	+ "txd_cnt<2>" * "txcnt16<1>" * "txcnt16<0>" * 
	"txcnt16<2>.FBK".LFBK * "txcnt16<3>.FBK".LFBK * "txd_shift<4>.FBK".LFBK * 
	/"txd_shift<3>.FBK".LFBK
	+ "txd_cnt<1>" * /"txd_cnt<3>" * "txcnt16<1>" * 
	"txcnt16<0>" * "txcnt16<2>.FBK".LFBK * "txcnt16<3>.FBK".LFBK * 
	"txd_shift<4>.FBK".LFBK * /"txd_shift<3>.FBK".LFBK
	+ "txd_cnt<1>" * /"txd_cnt<3>" * "txcnt16<1>" * 
	"txcnt16<0>" * "txcnt16<2>.FBK".LFBK * "txcnt16<3>.FBK".LFBK * 
	/"txd_shift<4>.FBK".LFBK * "txd_shift<3>.FBK".LFBK
	+ /"txd_cnt<1>" * "txd_cnt<3>" * "txcnt16<1>" * 
	"txcnt16<0>" * "txcnt16<2>.FBK".LFBK * "txcnt16<3>.FBK".LFBK * 
	/"txd_shift<4>.FBK".LFBK * "txd_shift<3>.FBK".LFBK
	+ "txd_cnt<3>" * "txcnt16<1>" * "txcnt16<0>" * 
	"txd_cnt<0>.FBK".LFBK * "txcnt16<2>.FBK".LFBK * "txcnt16<3>.FBK".LFBK * 
	/"txd_shift<4>.FBK".LFBK * "txd_shift<3>.FBK".LFBK
;Imported pterms FB1_12
	+ /"txd_cnt<1>" * "txd_cnt<3>" * "txcnt16<1>" * 
	"txcnt16<0>" * "txcnt16<2>.FBK".LFBK * "txcnt16<3>.FBK".LFBK * 
	"txd_shift<4>.FBK".LFBK * /"txd_shift<3>.FBK".LFBK
	+ "txd_cnt<3>" * "txcnt16<1>" * "txcnt16<0>" * 
	"txd_cnt<0>.FBK".LFBK * "txcnt16<2>.FBK".LFBK * "txcnt16<3>.FBK".LFBK * 
	"txd_shift<4>.FBK".LFBK * /"txd_shift<3>.FBK".LFBK
	+ /"txd_cnt<1>" * /"txd_cnt<2>" * /"txd_cnt<3>" * 
	"txcnt16<1>" * "txcnt16<0>" * "tbuf<3>" * "txd_cnt<0>.FBK".LFBK * 
	"txcnt16<2>.FBK".LFBK * "txcnt16<3>.FBK".LFBK * /"txd_shift<3>.FBK".LFBK
	+ /"txd_cnt<1>" * /"txd_cnt<2>" * /"txd_cnt<3>" * 
	"txcnt16<1>" * "txcnt16<0>" * /"tbuf<3>" * "txd_cnt<0>.FBK".LFBK * 
	"txcnt16<2>.FBK".LFBK * "txcnt16<3>.FBK".LFBK * "txd_shift<3>.FBK".LFBK
    "txd_shift<3>".CLKF  =  bclk.PIN
    "txd_shift<3>".RSTF  =  rst
    "txd_shift<3>".PRLD  =  GND    

 "txd_shift<4>".T  =  "txd_cnt<2>" * "txcnt16<1>" * "txcnt16<0>" * 
	"txcnt16<2>.FBK".LFBK * "txcnt16<3>.FBK".LFBK * "txd_shift<4>.FBK".LFBK * 
	/"txd_shift<5>.FBK".LFBK
	+ "txd_cnt<2>" * "txcnt16<1>" * "txcnt16<0>" * 
	"txcnt16<2>.FBK".LFBK * "txcnt16<3>.FBK".LFBK * /"txd_shift<4>.FBK".LFBK * 
	"txd_shift<5>.FBK".LFBK
	+ "txd_cnt<1>" * /"txd_cnt<3>" * "txcnt16<1>" * 
	"txcnt16<0>" * "txcnt16<2>.FBK".LFBK * "txcnt16<3>.FBK".LFBK * 
	"txd_shift<4>.FBK".LFBK * /"txd_shift<5>.FBK".LFBK
;Imported pterms FB1_9
	+ /"txd_cnt<1>" * "txd_cnt<3>" * "txcnt16<1>" * 
	"txcnt16<0>" * "txcnt16<2>.FBK".LFBK * "txcnt16<3>.FBK".LFBK * 
	"txd_shift<4>.FBK".LFBK * /"txd_shift<5>.FBK".LFBK
	+ "txd_cnt<3>" * "txcnt16<1>" * "txcnt16<0>" * 
	"txd_cnt<0>.FBK".LFBK * "txcnt16<2>.FBK".LFBK * "txcnt16<3>.FBK".LFBK * 
	"txd_shift<4>.FBK".LFBK * /"txd_shift<5>.FBK".LFBK
;Imported pterms FB1_11
	+ "txd_cnt<1>" * /"txd_cnt<3>" * "txcnt16<1>" * 
	"txcnt16<0>" * "txcnt16<2>.FBK".LFBK * "txcnt16<3>.FBK".LFBK * 
	/"txd_shift<4>.FBK".LFBK * "txd_shift<5>.FBK".LFBK
	+ /"txd_cnt<1>" * "txd_cnt<3>" * "txcnt16<1>" * 
	"txcnt16<0>" * "txcnt16<2>.FBK".LFBK * "txcnt16<3>.FBK".LFBK * 
	/"txd_shift<4>.FBK".LFBK * "txd_shift<5>.FBK".LFBK
	+ "txd_cnt<3>" * "txcnt16<1>" * "txcnt16<0>" * 
	"txd_cnt<0>.FBK".LFBK * "txcnt16<2>.FBK".LFBK * "txcnt16<3>.FBK".LFBK * 
	/"txd_shift<4>.FBK".LFBK * "txd_shift<5>.FBK".LFBK
	+ /"txd_cnt<1>" * /"txd_cnt<2>" * /"txd_cnt<3>" * 
	"txcnt16<1>" * "txcnt16<0>" * "tbuf<4>" * "txd_cnt<0>.FBK".LFBK * 
	"txcnt16<2>.FBK".LFBK * "txcnt16<3>.FBK".LFBK * /"txd_shift<4>.FBK".LFBK
	+ /"txd_cnt<1>" * /"txd_cnt<2>" * /"txd_cnt<3>" * 
	"txcnt16<1>" * "txcnt16<0>" * /"tbuf<4>" * "txd_cnt<0>.FBK".LFBK * 
	"txcnt16<2>.FBK".LFBK * "txcnt16<3>.FBK".LFBK * "txd_shift<4>.FBK".LFBK
    "txd_shift<4>".CLKF  =  bclk.PIN
    "txd_shift<4>".RSTF  =  rst
    "txd_shift<4>".PRLD  =  GND    

 "txd_shift<5>".T  =  "txd_cnt<2>" * "txcnt16<1>" * "txcnt16<0>" * 
	"txcnt16<2>.FBK".LFBK * "txcnt16<3>.FBK".LFBK * "txd_shift<6>.FBK".LFBK * 
	/"txd_shift<5>.FBK".LFBK
	+ "txd_cnt<2>" * "txcnt16<1>" * "txcnt16<0>" * 
	"txcnt16<2>.FBK".LFBK * "txcnt16<3>.FBK".LFBK * /"txd_shift<6>.FBK".LFBK * 
	"txd_shift<5>.FBK".LFBK
	+ "txd_cnt<1>" * /"txd_cnt<3>" * "txcnt16<1>" * 
	"txcnt16<0>" * "txcnt16<2>.FBK".LFBK * "txcnt16<3>.FBK".LFBK * 
	/"txd_shift<6>.FBK".LFBK * "txd_shift<5>.FBK".LFBK
;Imported pterms FB1_6
	+ "txd_cnt<1>" * /"txd_cnt<3>" * "txcnt16<1>" * 
	"txcnt16<0>" * "txcnt16<2>.FBK".LFBK * "txcnt16<3>.FBK".LFBK * 
	"txd_shift<6>.FBK".LFBK * /"txd_shift<5>.FBK".LFBK
	+ /"txd_cnt<1>" * "txd_cnt<3>" * "txcnt16<1>" * 
	"txcnt16<0>" * "txcnt16<2>.FBK".LFBK * "txcnt16<3>.FBK".LFBK * 
	"txd_shift<6>.FBK".LFBK * /"txd_shift<5>.FBK".LFBK
	+ /"txd_cnt<1>" * "txd_cnt<3>" * "txcnt16<1>" * 
	"txcnt16<0>" * "txcnt16<2>.FBK".LFBK * "txcnt16<3>.FBK".LFBK * 
	/"txd_shift<6>.FBK".LFBK * "txd_shift<5>.FBK".LFBK
	+ "txd_cnt<3>" * "txcnt16<1>" * "txcnt16<0>" * 
	"txd_cnt<0>.FBK".LFBK * "txcnt16<2>.FBK".LFBK * "txcnt16<3>.FBK".LFBK * 
	"txd_shift<6>.FBK".LFBK * /"txd_shift<5>.FBK".LFBK
	+ "txd_cnt<3>" * "txcnt16<1>" * "txcnt16<0>" * 
	"txd_cnt<0>.FBK".LFBK * "txcnt16<2>.FBK".LFBK * "txcnt16<3>.FBK".LFBK * 
	/"txd_shift<6>.FBK".LFBK * "txd_shift<5>.FBK".LFBK
;Imported pterms FB1_5
	+ /"txd_cnt<1>" * /"txd_cnt<2>" * /"txd_cnt<3>" * 
	"txcnt16<1>" * "txcnt16<0>" * "tbuf<5>" * "txd_cnt<0>.FBK".LFBK * 
	"txcnt16<2>.FBK".LFBK * "txcnt16<3>.FBK".LFBK * /"txd_shift<5>.FBK".LFBK
;Imported pterms FB1_8
	+ /"txd_cnt<1>" * /"txd_cnt<2>" * /"txd_cnt<3>" * 
	"txcnt16<1>" * "txcnt16<0>" * /"tbuf<5>" * "txd_cnt<0>.FBK".LFBK * 
	"txcnt16<2>.FBK".LFBK * "txcnt16<3>.FBK".LFBK * "txd_shift<5>.FBK".LFBK
    "txd_shift<5>".CLKF  =  bclk.PIN
    "txd_shift<5>".RSTF  =  rst
    "txd_shift<5>".PRLD  =  GND    

 "txd_shift<6>".T  =  "txd_cnt<2>" * "txcnt16<1>" * "txcnt16<0>" * 
	"txcnt16<2>.FBK".LFBK * "txcnt16<3>.FBK".LFBK * "txd_shift<6>.FBK".LFBK * 
	/"txd_shift<7>.FBK".LFBK
	+ "txd_cnt<2>" * "txcnt16<1>" * "txcnt16<0>" * 
	"txcnt16<2>.FBK".LFBK * "txcnt16<3>.FBK".LFBK * /"txd_shift<6>.FBK".LFBK * 
	"txd_shift<7>.FBK".LFBK
;Imported pterms FB1_4
	+ "txd_cnt<1>" * /"txd_cnt<3>" * "txcnt16<1>" * 
	"txcnt16<0>" * "txcnt16<2>.FBK".LFBK * "txcnt16<3>.FBK".LFBK * 
	"txd_shift<6>.FBK".LFBK * /"txd_shift<7>.FBK".LFBK
	+ "txd_cnt<1>" * /"txd_cnt<3>" * "txcnt16<1>" * 
	"txcnt16<0>" * "txcnt16<2>.FBK".LFBK * "txcnt16<3>.FBK".LFBK * 
	/"txd_shift<6>.FBK".LFBK * "txd_shift<7>.FBK".LFBK
	+ /"txd_cnt<1>" * "txd_cnt<3>" * "txcnt16<1>" * 
	"txcnt16<0>" * "txcnt16<2>.FBK".LFBK * "txcnt16<3>.FBK".LFBK * 
	"txd_shift<6>.FBK".LFBK * /"txd_shift<7>.FBK".LFBK
	+ /"txd_cnt<1>" * "txd_cnt<3>" * "txcnt16<1>" * 
	"txcnt16<0>" * "txcnt16<2>.FBK".LFBK * "txcnt16<3>.FBK".LFBK * 
	/"txd_shift<6>.FBK".LFBK * "txd_shift<7>.FBK".LFBK
	+ "txd_cnt<3>" * "txcnt16<1>" * "txcnt16<0>" * 
	"txd_cnt<0>.FBK".LFBK * "txcnt16<2>.FBK".LFBK * "txcnt16<3>.FBK".LFBK * 
	"txd_shift<6>.FBK".LFBK * /"txd_shift<7>.FBK".LFBK
;Imported pterms FB1_3
	+ "txd_cnt<3>" * "txcnt16<1>" * "txcnt16<0>" * 
	"txd_cnt<0>.FBK".LFBK * "txcnt16<2>.FBK".LFBK * "txcnt16<3>.FBK".LFBK * 
	/"txd_shift<6>.FBK".LFBK * "txd_shift<7>.FBK".LFBK
	+ /"txd_cnt<1>" * /"txd_cnt<2>" * /"txd_cnt<3>" * 
	"txcnt16<1>" * "txcnt16<0>" * "tbuf<6>" * "txd_cnt<0>.FBK".LFBK * 
	"txcnt16<2>.FBK".LFBK * "txcnt16<3>.FBK".LFBK * /"txd_shift<6>.FBK".LFBK
	+ /"txd_cnt<1>" * /"txd_cnt<2>" * /"txd_cnt<3>" * 
	"txcnt16<1>" * "txcnt16<0>" * /"tbuf<6>" * "txd_cnt<0>.FBK".LFBK * 
	"txcnt16<2>.FBK".LFBK * "txcnt16<3>.FBK".LFBK * "txd_shift<6>.FBK".LFBK
    "txd_shift<6>".CLKF  =  bclk.PIN
    "txd_shift<6>".RSTF  =  rst
    "txd_shift<6>".PRLD  =  GND    

 "txd_shift<7>".T  =  /"txd_cnt<1>" * /"txd_cnt<2>" * /"txd_cnt<3>" * 
	"txcnt16<1>" * "txcnt16<0>" * "tbuf<7>" * "txd_cnt<0>.FBK".LFBK * 
	"txcnt16<2>.FBK".LFBK * "txcnt16<3>.FBK".LFBK * /"txd_shift<7>.FBK".LFBK
	+ /"txd_cnt<1>" * /"txd_cnt<2>" * /"txd_cnt<3>" * 
	"txcnt16<1>" * "txcnt16<0>" * /"tbuf<7>" * "txd_cnt<0>.FBK".LFBK * 
	"txcnt16<2>.FBK".LFBK * "txcnt16<3>.FBK".LFBK * "txd_shift<7>.FBK".LFBK
    "txd_shift<7>".CLKF  =  bclk.PIN
    "txd_shift<7>".RSTF  =  rst
    "txd_shift<7>".PRLD  =  GND    

****************************  Device Pin Out ****************************

Device : XC9572-7-PC84


                                                                 r  r     
                                                                 b  b     
                                                                 u  u     
                                                                 f  f     
           T  c  T  G  T  T  T  T  T  T  T  T  T  T  T  T  T  V  <  <  T  
           I  l  I  N  I  I  I  I  I  I  I  I  I  I  I  I  I  C  7  6  I  
           E  k  E  D  E  E  E  E  E  E  E  E  E  E  E  E  E  C  >  >  E  
           --------------------------------------------------------------  
          /11 10 9  8  7  6  5  4  3  2  1  84 83 82 81 80 79 78 77 76 75 \
     TIE | 12                                                          74 | TIE
     TIE | 13                                                          73 | VCC
     TIE | 14                                                          72 | rbuf<5>
     TIE | 15                                                          71 | rbuf<3>
     GND | 16                                                          70 | rbuf<4>
     TIE | 17                                                          69 | rbuf<1>
     TIE | 18                                                          68 | rbuf<2>
     TIE | 19                                                          67 | TIE
     rst | 20                                                          66 | rbuf<0>
     TIE | 21                        XC9572-7-PC84                     65 | TIE
     VCC | 22                                                          64 | VCC
xmit_cmd | 23                                                          63 | rec_ready
     TIE | 24                                                          62 | xmit_done
     TIE | 25                                                          61 | bclk
     TIE | 26                                                          60 | GND
     GND | 27                                                          59 | TDO
     TDI | 28                                                          58 | TIE
     TMS | 29                                                          57 | TIE
     TCK | 30                                                          56 | rxd
     TIE | 31                                                          55 | TIE
     TIE | 32                                                          54 | TIE
         \ 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 /
           --------------------------------------------------------------  
           t  T  t  t  t  V  t  t  t  G  t  T  T  T  T  T  G  T  T  t  T  
           b  I  b  b  b  C  b  b  b  N  b  I  I  I  I  I  N  I  I  x  I  
           u  E  u  u  u  C  u  u  u  D  u  E  E  E  E  E  D  E  E  d  E  
           f     f  f  f     f  f  f     f                                
           <     <  <  <     <  <  <     <                                
           1     2  0  3     5  4  6     7                                
           >     >  >  >     >  >  >     >                                


Legend :  NC  = Not Connected, unbonded pin
         TIE  = Tie pin to GND or board trace driven to valid logic level
         VCC  = Dedicated Power Pin
         GND  = Dedicated Ground Pin
         TDI  = Test Data In, JTAG pin
         TDO  = Test Data Out, JTAG pin
         TCK  = Test Clock, JTAG pin
         TMS  = Test Mode Select, JTAG pin
         PE   = Port Enable pin
  PROHIBITED  = User reserved pin
****************************  Compiler Options  ****************************

Following is a list of all global compiler options used by the fitter run.

Device(s) Specified                         : XC9572-7-PC84
Use Timing Constraints                      : ON
Use Design Location Constraints             : ON
Create Programmable Ground Pins             : OFF
Use Advanced Fitting                        : ON
Use Local Feedback                          : ON
Use Pin Feedback                            : ON
Default Power Setting                       : STD
Default Output Slew Rate                    : FAST
Guide File Used                             : NONE
Multi Level Logic Optimization              : ON
Timing Optimization                         : ON
Power/Slew Optimization                     : OFF
High Fitting Effort                         : ON
Automatic Wire-ANDing                       : ON
Xor Synthesis                               : ON
D/T Synthesis                               : ON
Use Boolean Minimization                    : ON
Global Clock(GCK) Optimization              : ON
Global Set/Reset(GSR) Optimization          : ON
Global Output Enable(GTS) Optimization      : ON
Collapsing pterm limit                      : 25
Collapsing input limit                      : 36
12345

ex25.rpt - 源码说明

本页面展示了「[VHDL经典设计26例]--在xilinx芯片上调试通过--[01--1位全加器][02--2选1多路选择器][03--8位硬件加法器][04--7段数码显示译码器][05--8位串入并出寄存器][」中的 ex25.rpt 源码文件，采用 RPT 编程语言编写，共 1,248 行代码。您可以在线阅读完整代码内容，也可以返回资源详情页下载完整源码包进行本地学习和开发。

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