ex25.rpt
来自「[VHDL经典设计26例]--在xilinx芯片上调试通过--[01--1位全加」· RPT 代码 · 共 1,248 行 · 第 1/5 页
RPT
1,248 行
rxd_shift<7> XX........XXX@@@X@@X......XX............ 14 9
rxd_shift<6> XX........XXX@@@X@@X.....XX............. 14 9
rbuf<7> XX......X.XXX@@@X@@X......X............. 14 9
rxcnt16<0> X.........XXX...X@@X.......X............ 9 7
rxd_shift<4> XX........XXX@@@X@@X...XX............... 14 9
rxd_shift<5> XX........XXX@@@X@@X....XX.............. 14 9
rxd_shift<3> XX........XXX@@@X@@X..XX................ 14 9
rxd_shift<2> XX........XXX@@@X@@X.XX................. 14 9
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK/FCLK - Global clock
O - Output GTS/FOE - Global 3state/output-enable
(b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB3 ***********************************
Number of function block inputs used/remaining: 16/20
Number of signals used by logic mapping into function block: 16
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
baud_cnt<2> 2 0 /\3 0 FB3_1 STD 25 I/O (b)
(unused) 0 0 0 5 FB3_2 17 I/O
(unused) 0 0 0 5 FB3_3 31 I/O
(unused) 0 0 0 5 FB3_4 32 I/O
(unused) 0 0 0 5 FB3_5 19 I/O
(unused) 0 0 0 5 FB3_6 34 I/O
(unused) 0 0 0 5 FB3_7 35 I/O I
(unused) 0 0 0 5 FB3_8 21 I/O
(unused) 0 0 0 5 FB3_9 26 I/O
(unused) 0 0 0 5 FB3_10 40 I/O I
baud_cnt<0> 2 0 0 3 FB3_11 STD 33 I/O I
txcnt16<1> 3 0 0 2 FB3_12 STD 41 I/O I
txcnt16<0> 3 0 0 2 FB3_13 STD 43 I/O I
samples<0> 3 0 0 2 FB3_14 STD 36 I/O I
rxd_sync 4 0 \/1 0 FB3_15 STD 37 I/O I
rxcnt16<1> 5 1<- \/1 0 FB3_16 STD 45 I/O (b)
rxcnt16<2> 6 1<- 0 0 FB3_17 STD 39 I/O I
rxcnt16<3> 8 3<- 0 0 FB3_18 STD (b) (b)
Signals Used by Logic in Function Block
1: rst 7: "rxcnt16<1>.FBK".LFBK
12: "rxd_cnt<2>"
2: rxd 8: "rxcnt16<2>.FBK".LFBK
13: "rxd_cnt<3>"
3: "baud_cnt<0>.FBK".LFBK
9: "rxcnt16<3>.FBK".LFBK
14: rxd_sync.FBK.LFBK
4: "baud_cnt<1>" 10: "rxd_cnt<0>" 15: "samples<0>.FBK".LFBK
5: bclk.PIN 11: "rxd_cnt<1>" 16: "txcnt16<0>.FBK".LFBK
6: "rxcnt16<0>"
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
baud_cnt<2> X.XX.................................... 3 3
baud_cnt<0> X.X..................................... 2 2
txcnt16<1> X...X..........X........................ 3 3
txcnt16<0> X...X..........X........................ 3 3
samples<0> XX..X................................... 3 3
rxd_sync XX..X........XX......................... 5 5
rxcnt16<1> X...XXX..XXXXX.......................... 9 9
rxcnt16<2> X...XXXX.XXXXX.......................... 10 10
rxcnt16<3> X...XXXXXXXXXX.......................... 11 11
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK/FCLK - Global clock
O - Output GTS/FOE - Global 3state/output-enable
(b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB4 ***********************************
Number of function block inputs used/remaining: 31/5
Number of signals used by logic mapping into function block: 31
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
baud_cnt<4> 3 1<- /\3 0 FB4_1 STD 46 I/O (b)
txd_cnt<2> 3 0 /\1 1 FB4_2 STD 44 I/O (b)
rxd_cnt<2> 3 0 \/2 0 FB4_3 STD 51 I/O (b)
txd 11 6<- 0 0 FB4_4 STD 52 I/O O
baud_cnt<3> 3 2<- /\4 0 FB4_5 STD 47 I/O (b)
baud_cnt<1> 3 0 /\2 0 FB4_6 STD 54 I/O (b)
txd_cnt<3> 4 0 \/1 0 FB4_7 STD 55 I/O (b)
txd_cnt<1> 4 1<- \/2 0 FB4_8 STD 48 I/O (b)
rxd_cnt<1> 5 2<- \/2 0 FB4_9 STD 50 I/O (b)
rxd_cnt<3> 4 2<- \/3 0 FB4_10 STD 57 I/O (b)
rxd_cnt<0> 7 3<- \/1 0 FB4_11 STD 53 I/O (b)
rxd_shift<0> 10 5<- 0 0 FB4_12 STD 58 I/O (b)
bclk 4 3<- /\4 0 FB4_13 STD 61 I/O I/O
(unused) 0 0 /\3 2 FB4_14 56 I/O I
(unused) 0 0 0 5 FB4_15 65 I/O
xmit_done 3 0 \/2 0 FB4_16 STD 62 I/O I/O
rbuf<0> 3 2<- \/4 0 FB4_17 STD 66 I/O O
txd_shift<0> 12 7<- 0 0 FB4_18 STD (b) (b)
Signals Used by Logic in Function Block
1: N_bclk.FBK.LFBK 12: "rxcnt16<0>" 22: "txcnt16<0>"
2: "N_rbuf<0>.FBK".LFBK
13: "rxcnt16<1>" 23: "txcnt16<1>"
3: rst 14: "rxcnt16<2>" 24: "txcnt16<2>"
4: "tbuf<0>" 15: "rxcnt16<3>" 25: "txcnt16<3>"
5: N_txd.FBK.LFBK 16: "rxd_cnt<0>.FBK".LFBK
26: "txd_cnt<0>"
6: N_xmit_done.FBK.LFBK
17: "rxd_cnt<1>.FBK".LFBK
27: "txd_cnt<1>.FBK".LFBK
7: "baud_cnt<0>" 18: "rxd_cnt<2>.FBK".LFBK
28: "txd_cnt<2>.FBK".LFBK
8: "baud_cnt<1>.FBK".LFBK
19: "rxd_cnt<3>.FBK".LFBK
29: "txd_cnt<3>.FBK".LFBK
9: "baud_cnt<2>" 20: "rxd_shift<0>.FBK".LFBK
30: "txd_shift<0>.FBK".LFBK
10: "baud_cnt<3>.FBK".LFBK
21: "rxd_shift<1>" 31: "txd_shift<1>"
11: "baud_cnt<4>.FBK".LFBK
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
baud_cnt<4> ..X...XXXXX............................. 6 6
txd_cnt<2> X.X..................XXXXXX............. 8 8
rxd_cnt<2> X.X........XXXXXX....................... 8 8
txd X.X.X................XXXXXXXXX.......... 12 12
baud_cnt<3> ..X...XXXXX............................. 6 6
baud_cnt<1> ..X...XXXXX............................. 6 6
txd_cnt<3> X.X..................XXXXXXXX........... 10 10
txd_cnt<1> X.X..................XXXXXXXX........... 10 10
rxd_cnt<1> X.X........XXXXXXXX..................... 10 10
rxd_cnt<3> X.X........XXXXXXXX..................... 10 10
rxd_cnt<0> X.X........XXXXXXXX..................... 10 10
rxd_shift<0> X.X........XXXXXXXXXX................... 12 12
bclk X.X...XXXXX............................. 7 7
xmit_done X.X..X...............XXXXXXXX........... 11 11
rbuf<0> XXX........XXXXXXXXX.................... 12 12
txd_shift<0> X.XX.................XXXXXXXXXX......... 13 13
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK/FCLK - Global clock
O - Output GTS/FOE - Global 3state/output-enable
(b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
;;-----------------------------------------------------------------;;
; Implemented Equations.
FC_0_.OUT = /"rxd_cnt<1>" * /"rxd_cnt<2>" ; FC node
FC_1_.OUT = "rxcnt16<1>" * "rxcnt16<2>" * "rxcnt16<3>" ; FC node
bclk.T = ;Imported pterms FB4_14
"baud_cnt<0>" * "baud_cnt<2>" * N_bclk.FBK.LFBK *
"baud_cnt<1>.FBK".LFBK * "baud_cnt<3>.FBK".LFBK * "baud_cnt<4>.FBK".LFBK
+ "baud_cnt<0>" * /"baud_cnt<2>" * N_bclk.FBK.LFBK *
/"baud_cnt<1>.FBK".LFBK * "baud_cnt<3>.FBK".LFBK * "baud_cnt<4>.FBK".LFBK
+ "baud_cnt<0>" * /"baud_cnt<2>" * /N_bclk.FBK.LFBK *
"baud_cnt<1>.FBK".LFBK * "baud_cnt<3>.FBK".LFBK * /"baud_cnt<4>.FBK".LFBK
bclk.CLKF = clk ;FCLK/GCK
bclk.RSTF = rst
bclk.PRLD = GND
"rbuf<0>".T = ;Imported pterms FB4_16
/rst * "rxcnt16<0>" * "rxcnt16<1>" *
"rxcnt16<2>" * "rxcnt16<3>" * "rxd_cnt<0>.FBK".LFBK *
"rxd_cnt<3>.FBK".LFBK * "rxd_shift<0>.FBK".LFBK * /"rxd_cnt<1>.FBK".LFBK *
/"rxd_cnt<2>.FBK".LFBK * /"N_rbuf<0>.FBK".LFBK
+ /rst * "rxcnt16<0>" * "rxcnt16<1>" *
"rxcnt16<2>" * "rxcnt16<3>" * "rxd_cnt<0>.FBK".LFBK *
"rxd_cnt<3>.FBK".LFBK * /"rxd_shift<0>.FBK".LFBK * /"rxd_cnt<1>.FBK".LFBK *
/"rxd_cnt<2>.FBK".LFBK * "N_rbuf<0>.FBK".LFBK
"rbuf<0>".CLKF = N_bclk.FBK.LFBK
"rbuf<0>".PRLD = GND
"rbuf<1>".T = /rst * "rxd_cnt<0>" * "rxd_cnt<3>" * FC_0_.OUT *
FC_1_.OUT * "rxcnt16<0>.FBK".LFBK * "rxd_shift<1>.FBK".LFBK *
/"N_rbuf<1>.FBK".LFBK
+ /rst * "rxd_cnt<0>" * "rxd_cnt<3>" * FC_0_.OUT *
FC_1_.OUT * "rxcnt16<0>.FBK".LFBK * /"rxd_shift<1>.FBK".LFBK *
"N_rbuf<1>.FBK".LFBK
"rbuf<1>".CLKF = bclk.PIN
"rbuf<1>".PRLD = GND
"rbuf<2>".T = /rst * "rxd_cnt<0>" * "rxd_cnt<3>" * FC_0_.OUT *
FC_1_.OUT * "rxcnt16<0>.FBK".LFBK * "rxd_shift<2>.FBK".LFBK *
/"N_rbuf<2>.FBK".LFBK
;Imported pterms FB2_5
+ /rst * "rxd_cnt<0>" * "rxd_cnt<3>" * FC_0_.OUT *
FC_1_.OUT * "rxcnt16<0>.FBK".LFBK * /"rxd_shift<2>.FBK".LFBK *
"N_rbuf<2>.FBK".LFBK
"rbuf<2>".CLKF = bclk.PIN
"rbuf<2>".PRLD = GND
"rbuf<3>".T = /rst * "rxd_cnt<0>" * "rxd_cnt<3>" * FC_0_.OUT *
FC_1_.OUT * "rxcnt16<0>.FBK".LFBK * "rxd_shift<3>.FBK".LFBK *
/"N_rbuf<3>.FBK".LFBK
+ /rst * "rxd_cnt<0>" * "rxd_cnt<3>" * FC_0_.OUT *
FC_1_.OUT * "rxcnt16<0>.FBK".LFBK * /"rxd_shift<3>.FBK".LFBK *
"N_rbuf<3>.FBK".LFBK
"rbuf<3>".CLKF = bclk.PIN
"rbuf<3>".PRLD = GND
"rbuf<4>".T = /rst * "rxd_cnt<0>" * "rxd_cnt<3>" * FC_0_.OUT *
FC_1_.OUT * "rxcnt16<0>.FBK".LFBK * "rxd_shift<4>.FBK".LFBK *
/"N_rbuf<4>.FBK".LFBK
+ /rst * "rxd_cnt<0>" * "rxd_cnt<3>" * FC_0_.OUT *
FC_1_.OUT * "rxcnt16<0>.FBK".LFBK * /"rxd_shift<4>.FBK".LFBK *
"N_rbuf<4>.FBK".LFBK
"rbuf<4>".CLKF = bclk.PIN
"rbuf<4>".PRLD = GND
"rbuf<5>".T = ;Imported pterms FB2_7
/rst * "rxd_cnt<0>" * "rxd_cnt<3>" * FC_0_.OUT *
FC_1_.OUT * "rxcnt16<0>.FBK".LFBK * "rxd_shift<5>.FBK".LFBK *
/"N_rbuf<5>.FBK".LFBK
+ /rst * "rxd_cnt<0>" * "rxd_cnt<3>" * FC_0_.OUT *
FC_1_.OUT * "rxcnt16<0>.FBK".LFBK * /"rxd_shift<5>.FBK".LFBK *
"N_rbuf<5>.FBK".LFBK
"rbuf<5>".CLKF = bclk.PIN
"rbuf<5>".PRLD = GND
"rbuf<6>".T = /rst * "rxd_cnt<0>" * "rxd_cnt<3>" * FC_0_.OUT *
FC_1_.OUT * "rxcnt16<0>.FBK".LFBK * "rxd_shift<6>.FBK".LFBK *
/"N_rbuf<6>.FBK".LFBK
+ /rst * "rxd_cnt<0>" * "rxd_cnt<3>" * FC_0_.OUT *
FC_1_.OUT * "rxcnt16<0>.FBK".LFBK * /"rxd_shift<6>.FBK".LFBK *
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