ex25.rpt
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RPT
1,248 行
cpldfit: version E.38 Xilinx Inc.
Fitter Report
Design Name: ex25 Date: 3-12-2008, 9:08AM
Device Used: XC9572-7-PC84
Fitting Status: Successful
**************************** Resource Summary ****************************
Macrocells Product Terms Registers Pins Function Block
Used Used Used Used Inputs Used
51 /72 ( 70%) 293 /360 ( 81%) 51 /72 ( 70%) 24 /69 ( 34%) 96 /144 ( 66%)
PIN RESOURCES:
Signal Type Required Mapped | Pin Type Used Remaining
------------------------------------|---------------------------------------
Input : 11 11 | I/O : 21 42
Output : 10 10 | GCK/IO : 1 2
Bidirectional : 2 2 | GTS/IO : 2 0
GCK : 1 1 | GSR/IO : 0 1
GTS : 0 0 |
GSR : 0 0 |
---- ----
Total 24 24
MACROCELL RESOURCES:
Total Macrocells Available 72
Registered Macrocells 51
Non-registered Macrocell driving I/O 0
GLOBAL RESOURCES:
Signal 'clk' mapped onto global clock net GCK2.
Global output enable net(s) unused.
Global set/reset net(s) unused.
POWER DATA:
There are 51 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
There are a total of 51 macrocells used (MC).
End of Resource Summary
***************Resources Used by Successfully Mapped Logic******************
** LOGIC **
Signal Total Signals Loc Pwr Slew Pin Pin Pin
Name Pt Used Mode Rate # Type Use
baud_cnt<0> 2 2 FB3_11 STD 33 I/O I
baud_cnt<1> 3 6 FB4_6 STD 54 I/O (b)
baud_cnt<2> 2 3 FB3_1 STD 25 I/O (b)
baud_cnt<3> 3 6 FB4_5 STD 47 I/O (b)
baud_cnt<4> 3 6 FB4_1 STD 46 I/O (b)
bclk 4 7 FB4_13 STD FAST 61 I/O I/O
rbuf<0> 3 12 FB4_17 STD FAST 66 I/O O
rbuf<1> 3 14 FB2_2 STD FAST 69 I/O O
rbuf<2> 3 14 FB2_4 STD FAST 68 I/O O
rbuf<3> 3 14 FB2_6 STD FAST 71 I/O O
rbuf<4> 3 14 FB2_5 STD FAST 70 I/O O
rbuf<5> 3 14 FB2_8 STD FAST 72 I/O O
rbuf<6> 3 14 FB2_7 STD FAST 76 GTS/I/O O
rbuf<7> 3 14 FB2_11 STD FAST 77 GTS/I/O O
rec_ready 6 13 FB2_1 STD FAST 63 I/O O
rxcnt16<0> 3 9 FB2_12 STD 79 I/O (b)
rxcnt16<1> 5 9 FB3_16 STD 45 I/O (b)
rxcnt16<2> 6 10 FB3_17 STD 39 I/O I
rxcnt16<3> 8 11 FB3_18 STD (b) (b)
rxd_cnt<0> 7 10 FB4_11 STD 53 I/O (b)
rxd_cnt<1> 5 10 FB4_9 STD 50 I/O (b)
rxd_cnt<2> 3 8 FB4_3 STD 51 I/O (b)
rxd_cnt<3> 4 10 FB4_10 STD 57 I/O (b)
rxd_shift<0> 10 12 FB4_12 STD 58 I/O (b)
rxd_shift<1> 8 14 FB2_3 STD 67 I/O (b)
rxd_shift<2> 8 14 FB2_18 STD (b) (b)
rxd_shift<3> 8 14 FB2_17 STD 84 I/O (b)
rxd_shift<4> 8 14 FB2_13 STD 80 I/O (b)
rxd_shift<5> 8 14 FB2_14 STD 81 I/O (b)
rxd_shift<6> 8 14 FB2_10 STD 75 I/O (b)
rxd_shift<7> 8 14 FB2_9 STD 74 GSR/I/O (b)
rxd_sync 4 5 FB3_15 STD 37 I/O I
samples<0> 3 3 FB3_14 STD 36 I/O I
txcnt16<0> 3 3 FB3_13 STD 43 I/O I
txcnt16<1> 3 3 FB3_12 STD 41 I/O I
txcnt16<2> 3 4 FB1_1 STD 4 I/O (b)
txcnt16<3> 3 5 FB1_9 STD 9 GCK/I/O (b)
txd 11 12 FB4_4 STD FAST 52 I/O O
txd_cnt<0> 7 12 FB1_3 STD 6 I/O (b)
txd_cnt<1> 4 10 FB4_8 STD 48 I/O (b)
txd_cnt<2> 3 8 FB4_2 STD 44 I/O (b)
txd_cnt<3> 4 10 FB4_7 STD 55 I/O (b)
txd_shift<0> 12 13 FB4_18 STD (b) (b)
txd_shift<1> 12 13 FB1_18 STD 24 I/O (b)
txd_shift<2> 12 13 FB1_15 STD 14 I/O (b)
txd_shift<3> 12 13 FB1_14 STD 12 GCK/I/O (b)
txd_shift<4> 12 13 FB1_10 STD 13 I/O (b)
txd_shift<5> 12 13 FB1_7 STD 11 I/O (b)
txd_shift<6> 12 13 FB1_5 STD 2 I/O (b)
txd_shift<7> 4 12 FB1_8 STD 5 I/O (b)
xmit_done 3 11 FB4_16 STD FAST 62 I/O I/O
** INPUTS **
Signal Loc Pin Pin Pin
Name # Type Use
clk FB1_11 10 GCK/I/O GCK
rst FB1_13 20 I/O I
rxd FB4_14 56 I/O I
tbuf<0> FB3_14 36 I/O I
tbuf<1> FB3_11 33 I/O I
tbuf<2> FB3_7 35 I/O I
tbuf<3> FB3_15 37 I/O I
tbuf<4> FB3_10 40 I/O I
tbuf<5> FB3_17 39 I/O I
tbuf<6> FB3_12 41 I/O I
tbuf<7> FB3_13 43 I/O I
xmit_cmd FB1_16 23 I/O I
End of Resources Used by Successfully Mapped Logic
*********************Function Block Resource Summary***********************
Function # of FB Inputs Signals Total O/IO IO
Block Macrocells Used Used Pt Used Req Avail
FB1 10 26 26 89 0/0 18
FB2 16 23 28 86 8/0 17
FB3 9 16 16 36 0/0 17
FB4 16 31 31 82 2/2 17
---- ----- ----- -----
51 293 10/2 69
*********************************** FB1 ***********************************
Number of function block inputs used/remaining: 26/10
Number of signals used by logic mapping into function block: 26
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
txcnt16<2> 3 0 /\2 0 FB1_1 STD 4 I/O (b)
(unused) 0 0 \/5 0 FB1_2 1 I/O (b)
txd_cnt<0> 7 5<- \/3 0 FB1_3 STD 6 I/O (b)
(unused) 0 0 \/5 0 FB1_4 7 I/O (b)
txd_shift<6> 12 8<- \/1 0 FB1_5 STD 2 I/O (b)
(unused) 0 0 \/5 0 FB1_6 3 I/O (b)
txd_shift<5> 12 7<- 0 0 FB1_7 STD 11 I/O (b)
txd_shift<7> 4 0 /\1 0 FB1_8 STD 5 I/O (b)
txcnt16<3> 3 0 \/2 0 FB1_9 STD 9 GCK/I/O (b)
txd_shift<4> 12 7<- 0 0 FB1_10 STD 13 I/O (b)
(unused) 0 0 /\5 0 FB1_11 10 GCK/I/O GCK
(unused) 0 0 \/4 1 FB1_12 18 I/O (b)
(unused) 0 0 \/5 0 FB1_13 20 I/O I
txd_shift<3> 12 9<- \/2 0 FB1_14 STD 12 GCK/I/O (b)
txd_shift<2> 12 7<- 0 0 FB1_15 STD 14 I/O (b)
(unused) 0 0 /\5 0 FB1_16 23 I/O I
(unused) 0 0 \/5 0 FB1_17 15 I/O (b)
txd_shift<1> 12 7<- 0 0 FB1_18 STD 24 I/O (b)
Signals Used by Logic in Function Block
1: rst 10: bclk.PIN 19: "txd_shift<1>.FBK".LFBK
2: "tbuf<1>" 11: "txcnt16<0>" 20: "txd_shift<2>.FBK".LFBK
3: "tbuf<2>" 12: "txcnt16<1>" 21: "txd_shift<3>.FBK".LFBK
4: "tbuf<3>" 13: "txcnt16<2>.FBK".LFBK
22: "txd_shift<4>.FBK".LFBK
5: "tbuf<4>" 14: "txcnt16<3>.FBK".LFBK
23: "txd_shift<5>.FBK".LFBK
6: "tbuf<5>" 15: "txd_cnt<0>.FBK".LFBK
24: "txd_shift<6>.FBK".LFBK
7: "tbuf<6>" 16: "txd_cnt<1>" 25: "txd_shift<7>.FBK".LFBK
8: "tbuf<7>" 17: "txd_cnt<2>" 26: xmit_done.PIN
9: xmit_cmd 18: "txd_cnt<3>"
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
txcnt16<2> X........XXX............................ 4 4
txd_cnt<0> X.......XXXXXXXXXX.......X.............. 12 12
txd_shift<6> X.....X..XXXXXXXXX.....XX............... 13 13
txd_shift<5> X....X...XXXXXXXXX....XX................ 13 13
txd_shift<7> X......X.XXXXXXXXX......X............... 12 12
txcnt16<3> X........XXXX........................... 5 5
txd_shift<4> X...X....XXXXXXXXX...XX................. 13 13
txd_shift<3> X..X.....XXXXXXXXX..XX.................. 13 13
txd_shift<2> X.X......XXXXXXXXX.XX................... 13 13
txd_shift<1> XX.......XXXXXXXXXXX.................... 13 13
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK/FCLK - Global clock
O - Output GTS/FOE - Global 3state/output-enable
(b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB2 ***********************************
Number of function block inputs used/remaining: 23/13
Number of signals used by logic mapping into function block: 28
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
rec_ready 6 2<- /\1 0 FB2_1 STD 63 I/O O
rbuf<1> 3 0 /\2 0 FB2_2 STD 69 I/O O
rxd_shift<1> 8 3<- 0 0 FB2_3 STD 67 I/O (b)
rbuf<2> 3 1<- /\3 0 FB2_4 STD 68 I/O O
rbuf<4> 3 0 /\1 1 FB2_5 STD 70 I/O O
rbuf<3> 3 0 0 2 FB2_6 STD 71 I/O O
rbuf<6> 3 0 \/2 0 FB2_7 STD 76 GTS/I/O O
rbuf<5> 3 2<- \/4 0 FB2_8 STD 72 I/O O
rxd_shift<7> 8 4<- \/1 0 FB2_9 STD 74 GSR/I/O (b)
rxd_shift<6> 8 3<- 0 0 FB2_10 STD 75 I/O (b)
rbuf<7> 3 0 /\2 0 FB2_11 STD 77 GTS/I/O O
rxcnt16<0> 3 0 \/2 0 FB2_12 STD 79 I/O (b)
rxd_shift<4> 8 3<- 0 0 FB2_13 STD 80 I/O (b)
rxd_shift<5> 8 4<- /\1 0 FB2_14 STD 81 I/O (b)
(unused) 0 0 /\4 1 FB2_15 83 I/O (b)
(unused) 0 0 \/5 0 FB2_16 82 I/O (b)
rxd_shift<3> 8 5<- \/2 0 FB2_17 STD 84 I/O (b)
rxd_shift<2> 8 3<- 0 0 FB2_18 STD (b) (b)
Signals Used by Logic in Function Block
1: FC_0_.OUT 11: rst 20: "rxd_cnt<3>"
2: FC_1_.OUT 12: bclk.PIN 21: "rxd_shift<1>.FBK".LFBK
3: "N_rbuf<1>.FBK".LFBK
13: "rxcnt16<0>.FBK".LFBK
22: "rxd_shift<2>.FBK".LFBK
4: "N_rbuf<2>.FBK".LFBK
14: "rxcnt16<1>" 23: "rxd_shift<3>.FBK".LFBK
5: "N_rbuf<3>.FBK".LFBK
15: "rxcnt16<2>" 24: "rxd_shift<4>.FBK".LFBK
6: "N_rbuf<4>.FBK".LFBK
16: "rxcnt16<3>" 25: "rxd_shift<5>.FBK".LFBK
7: "N_rbuf<5>.FBK".LFBK
17: "rxd_cnt<0>" 26: "rxd_shift<6>.FBK".LFBK
8: "N_rbuf<6>.FBK".LFBK
18: "rxd_cnt<1>" 27: "rxd_shift<7>.FBK".LFBK
9: "N_rbuf<7>.FBK".LFBK
19: "rxd_cnt<2>" 28: rxd_sync
10: N_rec_ready.FBK.LFBK
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
rec_ready XX.......XXXX@@@X@@X.................... 13 8
rbuf<1> XXX.......XXX@@@X@@XX................... 14 9
rxd_shift<1> XX........XXX@@@X@@XXX.................. 14 9
rbuf<2> XX.X......XXX@@@X@@X.X.................. 14 9
rbuf<4> XX...X....XXX@@@X@@X...X................ 14 9
rbuf<3> XX..X.....XXX@@@X@@X..X................. 14 9
rbuf<6> XX.....X..XXX@@@X@@X.....X.............. 14 9
rbuf<5> XX....X...XXX@@@XXXX....X............... 14 11
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