ex25.tim
来自「[VHDL经典设计26例]--在xilinx芯片上调试通过--[01--1位全加」· TIM 代码 · 共 441 行 · 第 1/2 页
TIM
441 行
rbuf<7>.D 8.0
rec_ready.D
rxcnt16<0>.D 12.0
rxcnt16<1>.D 9.0
rxcnt16<2>.D 9.0
rxcnt16<3>.D 9.0
rxd_cnt<0>.D
rxd_cnt<1>.D
rxd_cnt<2>.D
rxd_cnt<3>.D
rxd_shift<0>.D
rxd_shift<1>.D
rxd_shift<2>.D
rxd_shift<3>.D
rxd_shift<4>.D 9.0
rxd_shift<5>.D 9.0 9.0
rxd_shift<6>.D 9.0 9.0
rxd_shift<7>.D 9.0 13.0
rxd_sync.D 8.0 8.0
txcnt16<0>.D 8.0
txcnt16<1>.D 8.0
txcnt16<2>.D 12.0 12.0
txcnt16<3>.D 12.0 12.0 8.0
txd.D 13.0 13.0 13.0 13.0 9.0 13.0
txd_cnt<0>.D 13.0 13.0 9.0 9.0 9.0
txd_cnt<1>.D 13.0 13.0 13.0 13.0 12.0
txd_cnt<2>.D 12.0 12.0 12.0 12.0 12.0
txd_cnt<3>.D 12.0 12.0 12.0 12.0 12.0
txd_shift<0>.D 13.0 13.0 13.0 13.0 13.0
txd_shift<1>.D 13.0 13.0 9.0 9.0 9.0
txd_shift<2>.D 13.0 13.0 9.0 9.0 9.0
txd_shift<3>.D 14.0 14.0 10.0 10.0 10.0
txd_shift<4>.D 13.0 13.0 9.0 9.0 9.0
txd_shift<5>.D 14.0 14.0 10.0 10.0 10.0
txd_shift<6>.D 14.0 14.0 10.0 10.0 10.0
txd_shift<7>.D 12.0 12.0 8.0 8.0 8.0
xmit_done.D 12.0 12.0 12.0 12.0 12.0
--------------------------------------------------------------------------------
Clock to Setup (tCYC) (nsec)
(Clock: N_bclk.Q)
\ From t t t t t t t t t t t
\ x x x x x x x x x x x
\ d d d d d d d d d d d
\ _ _ _ _ _ _ _ _ _ _ _
\ c c c s s s s s s s s
\ n n n h h h h h h h h
\ t t t i i i i i i i i
\ < < < f f f f f f f f
\ 1 2 3 t t t t t t t t
\ > > > < < < < < < < <
\ . . . 0 1 2 3 4 5 6 7
\ Q Q Q > > > > > > > >
\ . . . . . . . .
\ Q Q Q Q Q Q Q Q
To \------------------------------------------------------------------
rbuf<0>.D
rbuf<1>.D
rbuf<2>.D
rbuf<3>.D
rbuf<4>.D
rbuf<5>.D
rbuf<6>.D
rbuf<7>.D
rec_ready.D
rxcnt16<0>.D
rxcnt16<1>.D
rxcnt16<2>.D
rxcnt16<3>.D
rxd_cnt<0>.D
rxd_cnt<1>.D
rxd_cnt<2>.D
rxd_cnt<3>.D
rxd_shift<0>.D
rxd_shift<1>.D
rxd_shift<2>.D
rxd_shift<3>.D
rxd_shift<4>.D
rxd_shift<5>.D
rxd_shift<6>.D
rxd_shift<7>.D
rxd_sync.D
txcnt16<0>.D
txcnt16<1>.D
txcnt16<2>.D
txcnt16<3>.D
txd.D 9.0 9.0 9.0 9.0
txd_cnt<0>.D 13.0 13.0 13.0
txd_cnt<1>.D 9.0 9.0 9.0
txd_cnt<2>.D 8.0
txd_cnt<3>.D 8.0 8.0 8.0
txd_shift<0>.D 9.0 9.0 9.0 9.0 13.0
txd_shift<1>.D 13.0 13.0 13.0 9.0 9.0
txd_shift<2>.D 13.0 13.0 13.0 9.0 9.0
txd_shift<3>.D 14.0 14.0 14.0 10.0 10.0
txd_shift<4>.D 13.0 13.0 13.0 9.0 9.0
txd_shift<5>.D 14.0 14.0 14.0 10.0 9.0
txd_shift<6>.D 14.0 14.0 14.0 10.0 10.0
txd_shift<7>.D 12.0 12.0 12.0 8.0
xmit_done.D 8.0 8.0 8.0
--------------------------------------------------------------------------------
Clock to Setup (tCYC) (nsec)
(Clock: N_bclk.Q)
\ From x
\ m
\ i
\ t
\ _
\ d
\ o
\ n
\ e
\ .
\ Q
\
\
\
To \------
rbuf<0>.D
rbuf<1>.D
rbuf<2>.D
rbuf<3>.D
rbuf<4>.D
rbuf<5>.D
rbuf<6>.D
rbuf<7>.D
rec_ready.D
rxcnt16<0>.D
rxcnt16<1>.D
rxcnt16<2>.D
rxcnt16<3>.D
rxd_cnt<0>.D
rxd_cnt<1>.D
rxd_cnt<2>.D
rxd_cnt<3>.D
rxd_shift<0>.D
rxd_shift<1>.D
rxd_shift<2>.D
rxd_shift<3>.D
rxd_shift<4>.D
rxd_shift<5>.D
rxd_shift<6>.D
rxd_shift<7>.D
rxd_sync.D
txcnt16<0>.D
txcnt16<1>.D
txcnt16<2>.D
txcnt16<3>.D
txd.D
txd_cnt<0>.D 10.0
txd_cnt<1>.D
txd_cnt<2>.D
txd_cnt<3>.D
txd_shift<0>.D
txd_shift<1>.D
txd_shift<2>.D
txd_shift<3>.D
txd_shift<4>.D
txd_shift<5>.D
txd_shift<6>.D
txd_shift<7>.D
xmit_done.D 8.0
--------------------------------------------------------------------------------
Clock to Setup (tCYC) (nsec)
(Clock: clk)
\ From b b b b b b
\ a a a a a c
\ u u u u u l
\ d d d d d k
\ _ _ _ _ _ .
\ c c c c c Q
\ n n n n n
\ t t t t t
\ < < < < <
\ 0 1 2 3 4
\ > > > > >
\ . . . . .
\ Q Q Q Q Q
To \------------------------------------
baud_cnt<0>.D 8.0
baud_cnt<1>.D 12.0 8.0 12.0 8.0 8.0
baud_cnt<2>.D 8.0 12.0
baud_cnt<3>.D 13.0 9.0 13.0 9.0 9.0
baud_cnt<4>.D 13.0 9.0 13.0 9.0 8.0
bclk.D 13.0 9.0 13.0 9.0 9.0 9.0
Path Type Definition:
Pad to Pad (tPD) - Reports pad to pad paths that start
at input pads and end at output pads.
Paths are not traced through
registers.
Clock Pad to Output Pad (tCO) - Reports paths that start at input
pads trace through clock inputs of
registers and end at output pads.
Paths are not traced through PRE/CLR
inputs of registers.
Setup to Clock at Pad (tSU) - Reports external setup time of data
to clock at pad. Data path starts at
an input pad and end at register D/T
input. Clock path starts at input pad
and ends at the register clock input.
Paths are not traced through
registers.
Clock to Setup (tCYC) - Register to register cycle time.
Include source register tCO and
destination register tSU.
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