ex25.tim
来自「[VHDL经典设计26例]--在xilinx芯片上调试通过--[01--1位全加」· TIM 代码 · 共 441 行 · 第 1/2 页
TIM
441 行
Performance Summary Report
--------------------------
Design: ex25
Device: XC9572-7-PC84
Speed File: Version 3.0
Program: Timing Report Generator: version E.38
Date: Wed Mar 12 09:08:31 2008
Performance Summary:
Clock net 'bclk.Q' path delays:
Clock to Setup (tCYC) : 14.0ns (1 macrocell levels)
Clock to Q, net 'txd_cnt<1>.Q' to TFF Setup(D) at 'txd_shift<3>.D'(Pterm Clock)
Setup to Clock at the Pad (tSU) : 0.5ns (0 macrocell levels)
Data signal 'tbuf<0>' to TFF D input Pin at 'txd_shift<0>.D'
Clock pad 'bclk.Q' (Pterm Clock)
Minimum Clock Period: 14.0ns
Maximum Internal Clock Speed: 71.4Mhz
(Limited by Cycle Time)
Clock net 'clk' path delays:
Clock Pad to Output Pad (tCO) : 13.0ns (1 macrocell levels)
Clock Pad 'clk' to Output Pad 'rec_ready' (GCK)
Clock to Setup (tCYC) : 13.0ns (1 macrocell levels)
Clock to Q, net 'baud_cnt<0>.Q' to TFF Setup(D) at 'bclk.D' (GCK)
Target FF drives output net 'N_bclk$Q'
Minimum Clock Period: 13.0ns
Maximum Internal Clock Speed: 76.9Mhz
(Limited by Cycle Time)
--------------------------------------------------------------------------------
Clock Pad to Output Pad (tCO) (nsec)
\ From c
\ l
\ k
\
\
\
\
\
\
To \------
bclk 4.5
rbuf<0> 12.0
rbuf<1> 13.0
rbuf<2> 13.0
rbuf<3> 13.0
rbuf<4> 13.0
rbuf<5> 13.0
rbuf<6> 13.0
rbuf<7> 13.0
rec_ready 13.0
txd 12.0
xmit_done 12.0
--------------------------------------------------------------------------------
Clock to Setup (tCYC) (nsec)
(Clock: N_bclk.Q)
\ From r r r r r r r r r r r
\ b b b b b b b b e x x
\ u u u u u u u u c c c
\ f f f f f f f f _ n n
\ < < < < < < < < r t t
\ 0 1 2 3 4 5 6 7 e 1 1
\ > > > > > > > > a 6 6
\ . . . . . . . . d < <
\ Q Q Q Q Q Q Q Q y 0 1
\ . > >
\ Q . .
\ Q Q
\
\
To \------------------------------------------------------------------
rbuf<0>.D 9.0 13.0 13.0
rbuf<1>.D 8.0 8.0 12.0
rbuf<2>.D 9.0 9.0 13.0
rbuf<3>.D 8.0 8.0 12.0
rbuf<4>.D 8.0 8.0 12.0
rbuf<5>.D 9.0 9.0 13.0
rbuf<6>.D 8.0 8.0 12.0
rbuf<7>.D 8.0 8.0 12.0
rec_ready.D 9.0 9.0 13.0
rxcnt16<0>.D 8.0
rxcnt16<1>.D 12.0 8.0
rxcnt16<2>.D 12.0 8.0
rxcnt16<3>.D 13.0 9.0
rxd_cnt<0>.D 13.0 13.0
rxd_cnt<1>.D 13.0 13.0
rxd_cnt<2>.D 12.0 12.0
rxd_cnt<3>.D 13.0 13.0
rxd_shift<0>.D 13.0 13.0
rxd_shift<1>.D 9.0 13.0
rxd_shift<2>.D 9.0 13.0
rxd_shift<3>.D 9.0 13.0
rxd_shift<4>.D 9.0 13.0
rxd_shift<5>.D 9.0 13.0
rxd_shift<6>.D 9.0 13.0
rxd_shift<7>.D 9.0 13.0
rxd_sync.D
txcnt16<0>.D
txcnt16<1>.D
txcnt16<2>.D
txcnt16<3>.D
txd.D
txd_cnt<0>.D
txd_cnt<1>.D
txd_cnt<2>.D
txd_cnt<3>.D
txd_shift<0>.D
txd_shift<1>.D
txd_shift<2>.D
txd_shift<3>.D
txd_shift<4>.D
txd_shift<5>.D
txd_shift<6>.D
txd_shift<7>.D
xmit_done.D
--------------------------------------------------------------------------------
Clock to Setup (tCYC) (nsec)
(Clock: N_bclk.Q)
\ From r r r r r r r r r r r
\ x x x x x x x x x x x
\ c c d d d d d d d d d
\ n n _ _ _ _ _ _ _ _ _
\ t t c c c c s s s s s
\ 1 1 n n n n h h h h h
\ 6 6 t t t t i i i i i
\ < < < < < < f f f f f
\ 2 3 0 1 2 3 t t t t t
\ > > > > > > < < < < <
\ . . . . . . 0 1 2 3 4
\ Q Q Q Q Q Q > > > > >
\ . . . . .
\ Q Q Q Q Q
To \------------------------------------------------------------------
rbuf<0>.D 13.0 13.0 9.0 9.0 9.0 9.0 9.0
rbuf<1>.D 12.0 12.0 12.0 12.0 12.0 12.0 8.0
rbuf<2>.D 13.0 13.0 13.0 13.0 13.0 13.0 9.0
rbuf<3>.D 12.0 12.0 12.0 12.0 12.0 12.0 8.0
rbuf<4>.D 12.0 12.0 12.0 12.0 12.0 12.0 8.0
rbuf<5>.D 13.0 13.0 13.0 13.0 13.0 13.0
rbuf<6>.D 12.0 12.0 12.0 12.0 12.0 12.0
rbuf<7>.D 12.0 12.0 12.0 12.0 12.0 12.0
rec_ready.D 13.0 13.0 13.0 13.0 13.0 13.0
rxcnt16<0>.D 12.0 12.0 12.0 12.0
rxcnt16<1>.D 13.0 13.0 13.0 13.0
rxcnt16<2>.D 8.0 13.0 13.0 13.0 13.0
rxcnt16<3>.D 9.0 9.0 13.0 13.0 13.0 13.0
rxd_cnt<0>.D 13.0 13.0 9.0 9.0 9.0 8.0
rxd_cnt<1>.D 13.0 13.0 9.0 9.0 9.0 8.0
rxd_cnt<2>.D 12.0 12.0 8.0 8.0
rxd_cnt<3>.D 13.0 13.0 9.0 9.0 9.0 9.0
rxd_shift<0>.D 13.0 13.0 9.0 9.0 8.0 9.0 9.0 13.0
rxd_shift<1>.D 13.0 13.0 13.0 12.0 12.0 13.0 9.0 9.0
rxd_shift<2>.D 13.0 13.0 13.0 12.0 12.0 13.0 9.0 9.0
rxd_shift<3>.D 13.0 13.0 13.0 13.0 13.0 13.0 9.0 9.0
rxd_shift<4>.D 13.0 13.0 13.0 12.0 12.0 13.0 9.0
rxd_shift<5>.D 13.0 13.0 13.0 12.0 12.0 13.0
rxd_shift<6>.D 13.0 13.0 13.0 12.0 12.0 13.0
rxd_shift<7>.D 13.0 13.0 13.0 12.0 12.0 13.0
rxd_sync.D
txcnt16<0>.D
txcnt16<1>.D
txcnt16<2>.D
txcnt16<3>.D
txd.D
txd_cnt<0>.D
txd_cnt<1>.D
txd_cnt<2>.D
txd_cnt<3>.D
txd_shift<0>.D
txd_shift<1>.D
txd_shift<2>.D
txd_shift<3>.D
txd_shift<4>.D
txd_shift<5>.D
txd_shift<6>.D
txd_shift<7>.D
xmit_done.D
--------------------------------------------------------------------------------
Clock to Setup (tCYC) (nsec)
(Clock: N_bclk.Q)
\ From r r r r s t t t t t t
\ x x x x a x x x x x x
\ d d d d m c c c c d d
\ _ _ _ _ p n n n n . _
\ s s s s l t t t t Q c
\ h h h y e 1 1 1 1 n
\ i i i n s 6 6 6 6 t
\ f f f c < < < < < <
\ t t t . 0 0 1 2 3 0
\ < < < Q > > > > > >
\ 5 6 7 . . . . . .
\ > > > Q Q Q Q Q Q
\ . . .
\ Q Q Q
To \------------------------------------------------------------------
rbuf<0>.D
rbuf<1>.D
rbuf<2>.D
rbuf<3>.D
rbuf<4>.D
rbuf<5>.D 9.0
rbuf<6>.D 8.0
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