ex25.data

[VHDL经典设计26例]--在xilinx芯片上调试通过--[01--1位全加器][02--2选1多路选择器][03--8位硬件加法器][04--7段数码显示译码器][05--8位串入并出寄存器][

MODELDATA
MODELDATA_VERSION "v1998.8"
DESIGN "ex25";

/* port drive, load, max capacitance and max transition in data file */
PORTDATA
clk: MAXTRANS(0.0);
rst: MAXTRANS(0.0);
xmit_cmd: MAXTRANS(0.0);
rxd: MAXTRANS(0.0);
tbuf<0>: MAXTRANS(0.0);
tbuf<1>: MAXTRANS(0.0);
tbuf<2>: MAXTRANS(0.0);
tbuf<3>: MAXTRANS(0.0);
tbuf<4>: MAXTRANS(0.0);
tbuf<5>: MAXTRANS(0.0);
tbuf<6>: MAXTRANS(0.0);
tbuf<7>: MAXTRANS(0.0);
bclk: MAXTRANS(0.0);
xmit_done: MAXTRANS(0.0);
rec_ready: MAXTRANS(0.0);
txd: MAXTRANS(0.0);
rbuf<0>: MAXTRANS(0.0);
rbuf<1>: MAXTRANS(0.0);
rbuf<2>: MAXTRANS(0.0);
rbuf<3>: MAXTRANS(0.0);
rbuf<4>: MAXTRANS(0.0);
rbuf<5>: MAXTRANS(0.0);
rbuf<6>: MAXTRANS(0.0);
rbuf<7>: MAXTRANS(0.0);
ENDPORTDATA

/* timing arc data */
TIMINGDATA

ARCDATA
clk_bclk_delay:
CELL_RISE(scalar) {
  VALUES("4.5");
}
CELL_FALL(scalar) {
  VALUES("4.5");
}
ENDARCDATA

ARCDATA
clk_xmit_done_delay:
CELL_RISE(scalar) {
  VALUES("12");
}
CELL_FALL(scalar) {
  VALUES("12");
}
ENDARCDATA

ARCDATA
clk_rec_ready_delay:
CELL_RISE(scalar) {
  VALUES("13");
}
CELL_FALL(scalar) {
  VALUES("13");
}
ENDARCDATA

ARCDATA
clk_txd_delay:
CELL_RISE(scalar) {
  VALUES("12");
}
CELL_FALL(scalar) {
  VALUES("12");
}
ENDARCDATA

ARCDATA
clk_rbuf<0>_delay:
CELL_RISE(scalar) {
  VALUES("12");
}
CELL_FALL(scalar) {
  VALUES("12");
}
ENDARCDATA

ARCDATA
clk_rbuf<1>_delay:
CELL_RISE(scalar) {
  VALUES("13");
}
CELL_FALL(scalar) {
  VALUES("13");
}
ENDARCDATA

ARCDATA
clk_rbuf<2>_delay:
CELL_RISE(scalar) {
  VALUES("13");
}
CELL_FALL(scalar) {
  VALUES("13");
}
ENDARCDATA

ARCDATA
clk_rbuf<3>_delay:
CELL_RISE(scalar) {
  VALUES("13");
}
CELL_FALL(scalar) {
  VALUES("13");
}
ENDARCDATA

ARCDATA
clk_rbuf<4>_delay:
CELL_RISE(scalar) {
  VALUES("13");
}
CELL_FALL(scalar) {
  VALUES("13");
}
ENDARCDATA

ARCDATA
clk_rbuf<5>_delay:
CELL_RISE(scalar) {
  VALUES("13");
}
CELL_FALL(scalar) {
  VALUES("13");
}
ENDARCDATA

ARCDATA
clk_rbuf<6>_delay:
CELL_RISE(scalar) {
  VALUES("13");
}
CELL_FALL(scalar) {
  VALUES("13");
}
ENDARCDATA

ARCDATA
clk_rbuf<7>_delay:
CELL_RISE(scalar) {
  VALUES("13");
}
CELL_FALL(scalar) {
  VALUES("13");
}
ENDARCDATA

ENDTIMINGDATA
ENDMODELDATA