ex11_6.tim

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                           Performance Summary Report
                           --------------------------

Design:     ex11_6
Device:     XC9572-7-PC84
Speed File: Version 3.0
Program:    Timing Report Generator:  version E.38
Date:       Tue Mar 18 09:04:56 2008

Performance Summary: 

Clock net 'clk' path delays:

Clock Pad to Output Pad (tCO)             :         15.0ns (2 macrocell levels)
Clock Pad 'clk' to Output Pad 'col<8>'                                    (GCK)

Clock to Setup (tCYC)                     :          8.0ns (1 macrocell levels)
Clock to Q, net 'cnt<0>.Q' to DFF Setup(D) at 'cnt<0>.D'                  (GCK)
Target FF drives output net 'cnt<0>'

                          Minimum Clock Period: 8.0ns
                     Maximum Internal Clock Speed: 125.0Mhz
                         (Limited by Clock Pulse Width)

--------------------------------------------------------------------------------
                      Clock Pad to Output Pad (tCO) (nsec)

\ From      c
 \          l
  \         k
   \         
    \        
     \       
      \      
  To   \------

col<10>  15.0
col<11>  15.0
col<12>  15.0
col<13>  15.0
col<14>  15.0
col<15>  15.0
col<1>   11.0
col<2>   11.0
col<3>   15.0
col<4>   15.0
col<5>   15.0
col<6>   15.0
col<7>   15.0
col<8>   15.0
col<9>   15.0
row<0>   15.0
row<10>  15.0
row<11>  15.0
row<12>  15.0
row<13>  15.0
row<14>  15.0
row<15>  15.0
row<1>   15.0
row<2>   15.0
row<3>   15.0
row<4>   15.0
row<5>   15.0
row<6>   15.0
row<7>   15.0
row<8>   15.0
row<9>   15.0

--------------------------------------------------------------------------------
                          Clock to Setup (tCYC) (nsec)
                                  (Clock: clk)

\ From       c     c     c
 \           n     n     n
  \          t     t     t
   \         <     <     <
    \        0     1     2
     \       >     >     >
      \      .     .     .
       \     Q     Q     Q
  To    \------------------

cnt<0>.D   8.0            
cnt<1>.D   8.0            
cnt<2>.D   8.0   8.0      
cnt<3>.D   8.0   8.0   8.0

Path Type Definition: 

Pad to Pad (tPD) -                        Reports pad to pad paths that start 
                                          at input pads and end at output pads. 
                                          Paths are not traced through 
                                          registers. 

Clock Pad to Output Pad (tCO) -           Reports paths that start at input 
                                          pads trace through clock inputs of 
                                          registers and end at output pads. 
                                          Paths are not traced through PRE/CLR 
                                          inputs of registers. 

Setup to Clock at Pad (tSU) -             Reports external setup time of data 
                                          to clock at pad. Data path starts at 
                                          an input pad and end at register D/T 
                                          input. Clock path starts at input pad 
                                          and ends at the register clock input. 
                                          Paths are not traced through 
                                          registers. 

Clock to Setup (tCYC) -                   Register to register cycle time. 
                                          Include source register tCO and 
                                          destination register tSU.