ex11_6.mod

来自「[VHDL经典设计26例]--在xilinx芯片上调试通过--[01--1位全加」· MOD 代码 · 共 76 行

MODEL
MODEL_VERSION "v1998.8";
DESIGN "ex11_6";

/* port names and type */
INPUT S:PIN10 = clk;
OUTPUT S:PIN45 = col<8>;
OUTPUT S:PIN72 = row<13>;
OUTPUT S:PIN51 = col<12>;
OUTPUT S:PIN71 = row<11>;
OUTPUT S:PIN76 = row<14>;
OUTPUT S:PIN52 = row<1>;
OUTPUT S:PIN70 = row<12>;
OUTPUT S:PIN48 = col<11>;
OUTPUT S:PIN47 = col<10>;
OUTPUT S:PIN58 = row<2>;
OUTPUT S:PIN66 = row<8>;
OUTPUT S:PIN77 = row<15>;
OUTPUT S:PIN26 = col<4>;
OUTPUT S:PIN34 = col<6>;
OUTPUT S:PIN61 = row<3>;
OUTPUT S:PIN63 = row<4>;
OUTPUT S:PIN62 = row<5>;
OUTPUT S:PIN65 = row<6>;
OUTPUT S:PIN67 = row<7>;
OUTPUT S:PIN69 = row<9>;
OUTPUT S:PIN68 = row<10>;
OUTPUT S:PIN46 = col<9>;
OUTPUT S:PIN53 = col<13>;
OUTPUT S:PIN24 = col<2>;
OUTPUT S:PIN25 = col<3>;
OUTPUT S:PIN56 = row<0>;
OUTPUT S:PIN32 = col<7>;
OUTPUT S:PIN31 = col<5>;
OUTPUT S:PIN57 = col<15>;
OUTPUT S:PIN55 = col<14>;
OUTPUT S:PIN23 = col<1>;
OUTPUT S:PIN20 = col<0>;

/* timing arc definitions */
clk_col<8>_delay: DELAY clk col<8>;
clk_row<13>_delay: DELAY clk row<13>;
clk_col<12>_delay: DELAY clk col<12>;
clk_row<11>_delay: DELAY clk row<11>;
clk_row<14>_delay: DELAY clk row<14>;
clk_row<1>_delay: DELAY clk row<1>;
clk_row<12>_delay: DELAY clk row<12>;
clk_col<11>_delay: DELAY clk col<11>;
clk_col<10>_delay: DELAY clk col<10>;
clk_row<2>_delay: DELAY clk row<2>;
clk_row<8>_delay: DELAY clk row<8>;
clk_row<15>_delay: DELAY clk row<15>;
clk_col<4>_delay: DELAY clk col<4>;
clk_col<6>_delay: DELAY clk col<6>;
clk_row<3>_delay: DELAY clk row<3>;
clk_row<4>_delay: DELAY clk row<4>;
clk_row<5>_delay: DELAY clk row<5>;
clk_row<6>_delay: DELAY clk row<6>;
clk_row<7>_delay: DELAY clk row<7>;
clk_row<9>_delay: DELAY clk row<9>;
clk_row<10>_delay: DELAY clk row<10>;
clk_col<9>_delay: DELAY clk col<9>;
clk_col<13>_delay: DELAY clk col<13>;
clk_col<2>_delay: DELAY clk col<2>;
clk_col<3>_delay: DELAY clk col<3>;
clk_row<0>_delay: DELAY clk row<0>;
clk_col<7>_delay: DELAY clk col<7>;
clk_col<5>_delay: DELAY clk col<5>;
clk_col<15>_delay: DELAY clk col<15>;
clk_col<14>_delay: DELAY clk col<14>;
clk_col<1>_delay: DELAY clk col<1>;

/* timing check arc definitions */

ENDMODEL