ex11_6.rpt
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RPT
518 行
(b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB4 ***********************************
Number of function block inputs used/remaining: 4/32
Number of signals used by logic mapping into function block: 4
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
col<9> 4 0 0 1 FB4_1 STD 46 I/O O
(unused) 0 0 0 5 FB4_2 44 I/O
col<12> 2 0 0 3 FB4_3 STD 51 I/O O
row<1> 1 0 0 4 FB4_4 STD 52 I/O O
col<10> 3 0 0 2 FB4_5 STD 47 I/O O
(unused) 0 0 0 5 FB4_6 54 I/O
col<14> 1 0 0 4 FB4_7 STD 55 I/O O
col<11> 3 0 0 2 FB4_8 STD 48 I/O O
(unused) 0 0 0 5 FB4_9 50 I/O
col<15> 1 0 0 4 FB4_10 STD 57 I/O O
col<13> 3 0 0 2 FB4_11 STD 53 I/O O
row<2> 1 0 0 4 FB4_12 STD 58 I/O O
row<3> 1 0 0 4 FB4_13 STD 61 I/O O
row<0> 1 0 0 4 FB4_14 STD 56 I/O O
row<6> 1 0 0 4 FB4_15 STD 65 I/O O
row<5> 1 0 0 4 FB4_16 STD 62 I/O O
row<8> 1 0 0 4 FB4_17 STD 66 I/O O
(unused) 0 0 0 5 FB4_18 (b)
Signals Used by Logic in Function Block
1: "cnt<0>" 3: "cnt<2>" 4: "cnt<3>"
2: "cnt<1>"
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
col<9> XXXX.................................... 4 4
col<12> XXXX.................................... 4 4
row<1> XXXX.................................... 4 4
col<10> XXXX.................................... 4 4
col<14> XXXX.................................... 4 4
col<11> XXXX.................................... 4 4
col<15> XXXX.................................... 4 4
col<13> XXXX.................................... 4 4
row<2> XXXX.................................... 4 4
row<3> XXXX.................................... 4 4
row<0> XXXX.................................... 4 4
row<6> XXXX.................................... 4 4
row<5> XXXX.................................... 4 4
row<8> XXXX.................................... 4 4
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK/FCLK - Global clock
O - Output GTS/FOE - Global 3state/output-enable
(b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
;;-----------------------------------------------------------------;;
; Implemented Equations.
"col<11>" = /"cnt<0>" * "cnt<1>" * /"cnt<2>"
+ /"cnt<0>" * /"cnt<2>" * "cnt<3>"
+ "cnt<0>" * /"cnt<1>" * "cnt<2>" * /"cnt<3>"
"col<7>" = /"cnt<0>" * "cnt<1>" * /"cnt<2>"
+ /"cnt<0>" * /"cnt<2>" * "cnt<3>"
+ "cnt<0>" * /"cnt<1>" * "cnt<2>" * /"cnt<3>"
/"col<8>" = "cnt<0>" * "cnt<1>" * "cnt<2>"
+ /"cnt<0>" * "cnt<2>" * /"cnt<3>"
"col<9>" = "cnt<0>" * "cnt<2>" * /"cnt<3>"
+ /"cnt<0>" * "cnt<1>" * /"cnt<2>"
+ /"cnt<0>" * /"cnt<2>" * "cnt<3>"
+ /"cnt<1>" * "cnt<2>" * /"cnt<3>"
"col<12>" = /"cnt<0>" * "cnt<1>" * /"cnt<2>"
+ "cnt<0>" * /"cnt<1>" * "cnt<2>" * /"cnt<3>"
/"col<13>" = "cnt<0>" * /"cnt<2>" * /"cnt<3>"
+ /"cnt<0>" * /"cnt<1>" * /"cnt<3>"
+ "cnt<0>" * "cnt<1>" * "cnt<2>" * "cnt<3>"
/"col<2>" = /"cnt<0>.FBK".LFBK * /"cnt<1>.FBK".LFBK *
/"cnt<3>.FBK".LFBK
+ "cnt<1>.FBK".LFBK * "cnt<2>.FBK".LFBK *
"cnt<3>.FBK".LFBK
+ "cnt<0>.FBK".LFBK * "cnt<1>.FBK".LFBK *
/"cnt<2>.FBK".LFBK * /"cnt<3>.FBK".LFBK
"col<3>" = /"cnt<0>" * "cnt<1>" * /"cnt<2>"
+ /"cnt<0>" * "cnt<1>" * "cnt<3>"
+ "cnt<0>" * /"cnt<1>" * "cnt<2>" * /"cnt<3>"
"col<4>" = "cnt<0>" * /"cnt<1>" * "cnt<2>"
+ /"cnt<0>" * "cnt<1>" * /"cnt<2>"
+ /"cnt<0>" * /"cnt<2>" * "cnt<3>"
"col<10>" = /"cnt<0>" * "cnt<1>" * /"cnt<3>"
+ /"cnt<0>" * /"cnt<2>" * "cnt<3>"
+ "cnt<0>" * /"cnt<1>" * "cnt<2>" * /"cnt<3>"
"col<5>" = /"cnt<0>" * "cnt<1>" * /"cnt<3>"
+ /"cnt<0>" * /"cnt<2>" * "cnt<3>"
+ "cnt<0>" * /"cnt<1>" * "cnt<2>" * /"cnt<3>"
"col<6>" = "cnt<0>" * "cnt<2>" * /"cnt<3>"
+ /"cnt<0>" * "cnt<1>" * /"cnt<2>"
+ /"cnt<0>" * /"cnt<2>" * "cnt<3>"
"row<0>" = "cnt<0>" * "cnt<1>" * "cnt<2>" * "cnt<3>"
"row<1>" = /"cnt<0>" * "cnt<1>" * "cnt<2>" * "cnt<3>"
"row<2>" = "cnt<0>" * /"cnt<1>" * "cnt<2>" * "cnt<3>"
"row<3>" = /"cnt<0>" * /"cnt<1>" * "cnt<2>" * "cnt<3>"
"row<4>" = "cnt<0>" * "cnt<1>" * /"cnt<2>" * "cnt<3>"
"row<5>" = /"cnt<0>" * "cnt<1>" * /"cnt<2>" * "cnt<3>"
"row<6>" = "cnt<0>" * /"cnt<1>" * /"cnt<2>" * "cnt<3>"
"row<7>" = /"cnt<0>" * /"cnt<1>" * /"cnt<2>" * "cnt<3>"
"row<8>" = "cnt<0>" * "cnt<1>" * "cnt<2>" * /"cnt<3>"
"row<9>" = /"cnt<0>" * "cnt<1>" * "cnt<2>" * /"cnt<3>"
"row<10>" = "cnt<0>" * /"cnt<1>" * "cnt<2>" * /"cnt<3>"
"row<11>" = /"cnt<0>" * /"cnt<1>" * "cnt<2>" * /"cnt<3>"
"row<12>" = "cnt<0>" * "cnt<1>" * /"cnt<2>" * /"cnt<3>"
"row<13>" = /"cnt<0>" * "cnt<1>" * /"cnt<2>" * /"cnt<3>"
"col<15>" = /"cnt<0>" * "cnt<1>" * /"cnt<2>" * /"cnt<3>"
"col<14>" = /"cnt<0>" * "cnt<1>" * /"cnt<2>" * /"cnt<3>"
"col<1>" = /"cnt<0>.FBK".LFBK * "cnt<1>.FBK".LFBK *
/"cnt<2>.FBK".LFBK * /"cnt<3>.FBK".LFBK
"row<14>" = "cnt<0>" * /"cnt<1>" * /"cnt<2>" * /"cnt<3>"
"col<0>" = Gnd
"cnt<0>" := /"cnt<0>.FBK".LFBK
"cnt<0>".CLKF = clk ;FCLK/GCK
"cnt<0>".PRLD = GND
"cnt<1>".T = "cnt<0>.FBK".LFBK
"cnt<1>".CLKF = clk ;FCLK/GCK
"cnt<1>".PRLD = GND
"cnt<2>".T = "cnt<0>.FBK".LFBK * "cnt<1>.FBK".LFBK
"cnt<2>".CLKF = clk ;FCLK/GCK
"cnt<2>".PRLD = GND
"cnt<3>".T = "cnt<0>.FBK".LFBK * "cnt<1>.FBK".LFBK *
"cnt<2>.FBK".LFBK
"cnt<3>".CLKF = clk ;FCLK/GCK
"cnt<3>".PRLD = GND
"row<15>" = /"cnt<0>" * /"cnt<1>" * /"cnt<2>" * /"cnt<3>"
**************************** Device Pin Out ****************************
Device : XC9572-7-PC84
r r
o o
w w
< <
T c T G T T T T T T T T T T T T T V 1 1 T
I l I N I I I I I I I I I I I I I C 5 4 I
E k E D E E E E E E E E E E E E E C > > E
--------------------------------------------------------------
/11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 \
TIE | 12 74 | TIE
TIE | 13 73 | VCC
TIE | 14 72 | row<13>
TIE | 15 71 | row<11>
GND | 16 70 | row<12>
TIE | 17 69 | row<9>
TIE | 18 68 | row<10>
TIE | 19 67 | row<7>
col<0> | 20 66 | row<8>
TIE | 21 XC9572-7-PC84 65 | row<6>
VCC | 22 64 | VCC
col<1> | 23 63 | row<4>
col<2> | 24 62 | row<5>
col<3> | 25 61 | row<3>
col<4> | 26 60 | GND
GND | 27 59 | TDO
TDI | 28 58 | row<2>
TMS | 29 57 | col<15>
TCK | 30 56 | row<0>
col<5> | 31 55 | col<14>
col<7> | 32 54 | TIE
\ 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 /
--------------------------------------------------------------
T c T T T V T T T G T T c c c c G T c r c
I o I I I C I I I N I I o o o o N I o o o
E l E E E C E E E D E E l l l l D E l w l
< < < < < < < <
6 8 9 1 1 1 1 1
> > > 0 1 2 > 3
> > > >
Legend : NC = Not Connected, unbonded pin
TIE = Tie pin to GND or board trace driven to valid logic level
VCC = Dedicated Power Pin
GND = Dedicated Ground Pin
TDI = Test Data In, JTAG pin
TDO = Test Data Out, JTAG pin
TCK = Test Clock, JTAG pin
TMS = Test Mode Select, JTAG pin
PE = Port Enable pin
PROHIBITED = User reserved pin
**************************** Compiler Options ****************************
Following is a list of all global compiler options used by the fitter run.
Device(s) Specified : XC9572-7-PC84
Use Timing Constraints : ON
Use Design Location Constraints : ON
Create Programmable Ground Pins : OFF
Use Advanced Fitting : ON
Use Local Feedback : ON
Use Pin Feedback : ON
Default Power Setting : STD
Default Output Slew Rate : FAST
Guide File Used : NONE
Multi Level Logic Optimization : ON
Timing Optimization : ON
Power/Slew Optimization : OFF
High Fitting Effort : ON
Automatic Wire-ANDing : ON
Xor Synthesis : ON
D/T Synthesis : ON
Use Boolean Minimization : ON
Global Clock(GCK) Optimization : ON
Global Set/Reset(GSR) Optimization : ON
Global Output Enable(GTS) Optimization : ON
Collapsing pterm limit : 25
Collapsing input limit : 36
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