ex11_6.gyd

来自「[VHDL经典设计26例]--在xilinx芯片上调试通过--[01--1位全加」· GYD 代码 · 共 63 行

Pin Freeze File:  version E.38

957284 XC9572-7-PC84
clk S:PIN10
col<11> S:PIN48
col<7> S:PIN32
col<8> S:PIN45
col<9> S:PIN46
col<12> S:PIN51
col<13> S:PIN53
col<2> S:PIN24
col<3> S:PIN25
col<4> S:PIN26
col<10> S:PIN47
col<5> S:PIN31
col<6> S:PIN34
row<0> S:PIN56
row<1> S:PIN52
row<2> S:PIN58
row<3> S:PIN61
row<4> S:PIN63
row<5> S:PIN62
row<6> S:PIN65
row<7> S:PIN67
row<8> S:PIN66
row<9> S:PIN69
row<10> S:PIN68
row<11> S:PIN71
row<12> S:PIN70
row<13> S:PIN72
col<15> S:PIN57
col<14> S:PIN55
col<1> S:PIN23
row<14> S:PIN76
col<0> S:PIN20
row<15> S:PIN77


;The remaining section of the .gyd file is for documentation purposes only.
;It shows where your internal equations were placed in the last successful fit.

PARTITION FB1_12 "cnt<3>" "N_col<0>" "cnt<2>" "cnt<1>"
		 "N53$BUF2" "cnt<0>" "C0/N42"
PARTITION FB2_1 N35 N45 N41 N47
		 N51 N49 N55 N53
		
PARTITION FB2_11 net1

PARTITION FB3_1 "C0/N56"
PARTITION FB3_3 "C0/N84$BUF0" "C0/N112$BUF0"
PARTITION FB3_6 "C0/N98"
PARTITION FB3_9 "C0/N70"
PARTITION FB3_16 "C0/N126"

PARTITION FB4_1 "C0/N140"
PARTITION FB4_3 "C0/N156" N29 "C0/N84"
PARTITION FB4_7 "N53$BUF1" "C0/N112"
PARTITION FB4_10 "N53$BUF0" "C0/N170" N31 N33
		 N28 N39 N37 N43