time_sim.edn

来自「[VHDL经典设计26例]--在xilinx芯片上调试通过--[01--1位全加」· EDN 代码 · 共 1,614 行 · 第 1/5 页

(edif ex11_6
  (edifVersion 2 0 0)
  (edifLevel 0)
  (keywordMap (keywordLevel 0))
  (status
    (written
      (timestamp 2008 3 18 9 4 58)
      (program "Xilinx ngd2edif" (version "E.38"))
      (comment "Command line: -w -v fndtn ex11_6.nga time_sim.edn ")))
  (external SIMPRIMS
    (edifLevel 0)
    (technology (numberDefinition
      (scale 1 (E 1 -12) (unit TIME))))
    (cell x_opad
      (cellType GENERIC)
        (view view_1
          (viewType NETLIST)
          (interface
            (port PAD
              (direction OUTPUT)
            )
          )
      )
    )
    (cell x_buf
      (cellType GENERIC)
        (view view_1
          (viewType NETLIST)
          (interface
            (port IN
              (direction INPUT)
            )
            (port OUT
              (direction OUTPUT)
            )
          )
      )
    )
    (cell x_zero
      (cellType GENERIC)
        (view view_1
          (viewType NETLIST)
          (interface
            (port OUT
              (direction OUTPUT)
            )
          )
      )
    )
    (cell x_or2
      (cellType GENERIC)
        (view view_1
          (viewType NETLIST)
          (interface
            (port IN0
              (direction INPUT)
            )
            (port IN1
              (direction INPUT)
            )
            (port OUT
              (direction OUTPUT)
            )
          )
      )
    )
    (cell x_and3
      (cellType GENERIC)
        (view view_1
          (viewType NETLIST)
          (interface
            (port IN0
              (direction INPUT)
            )
            (port IN1
              (direction INPUT)
            )
            (port IN2
              (direction INPUT)
            )
            (port OUT
              (direction OUTPUT)
            )
          )
      )
    )
    (cell x_xor2
      (cellType GENERIC)
        (view view_1
          (viewType NETLIST)
          (interface
            (port IN0
              (direction INPUT)
            )
            (port IN1
              (direction INPUT)
            )
            (port OUT
              (direction OUTPUT)
            )
          )
      )
    )
    (cell x_ff
      (cellType GENERIC)
        (view view_1
          (viewType NETLIST)
          (interface
            (port IN
              (direction INPUT)
            )
            (port CE
              (direction INPUT)
            )
            (port CLK
              (direction INPUT)
            )
            (port SET
              (direction INPUT)
            )
            (port RST
              (direction INPUT)
            )
            (port OUT
              (direction OUTPUT)
            )
          )
      )
    )
    (cell x_one
      (cellType GENERIC)
        (view view_1
          (viewType NETLIST)
          (interface
            (port OUT
              (direction OUTPUT)
            )
          )
      )
    )
    (cell x_and2
      (cellType GENERIC)
        (view view_1
          (viewType NETLIST)
          (interface
            (port IN0
              (direction INPUT)
            )
            (port IN1
              (direction INPUT)
            )
            (port OUT
              (direction OUTPUT)
            )
          )
      )
    )
    (cell x_ipad
      (cellType GENERIC)
        (view view_1
          (viewType NETLIST)
          (interface
            (port PAD
              (direction INPUT)
            )
          )
      )
    )
    (cell x_and4
      (cellType GENERIC)
        (view view_1
          (viewType NETLIST)
          (interface
            (port IN0
              (direction INPUT)
            )
            (port IN1
              (direction INPUT)
            )
            (port IN2
              (direction INPUT)
            )
            (port IN3
              (direction INPUT)
            )
            (port OUT
              (direction OUTPUT)
            )
          )
      )
    )
    (cell x_or3
      (cellType GENERIC)
        (view view_1
          (viewType NETLIST)
          (interface
            (port IN0
              (direction INPUT)
            )
            (port IN1
              (direction INPUT)
            )
            (port IN2
              (direction INPUT)
            )
            (port OUT
              (direction OUTPUT)
            )
          )
      )
    )
    (cell x_or4
      (cellType GENERIC)
        (view view_1
          (viewType NETLIST)
          (interface
            (port IN0
              (direction INPUT)
            )
            (port IN1
              (direction INPUT)
            )
            (port IN2
              (direction INPUT)
            )
            (port IN3
              (direction INPUT)
            )
            (port OUT
              (direction OUTPUT)
            )
          )
      )
    )
    (cell x_inv
      (cellType GENERIC)
        (view view_1
          (viewType NETLIST)
          (interface
            (port IN
              (direction INPUT)
            )
            (port OUT
              (direction OUTPUT)
            )
          )
      )
    )
  )

  (library ex11_6_lib
    (edifLevel 0)
    (technology (numberDefinition
      (scale 1 (E 1 -12) (unit TIME))))
    (cell ex11_6
      (cellType GENERIC)
        (view view_1
          (viewType NETLIST)
          (interface
            (port (rename col_8__ "col<8>")
              (direction OUTPUT)
              (designator "45")
            )
            (port (rename row_13__ "row<13>")
              (direction OUTPUT)
              (designator "72")
            )
            (port (rename col_12__ "col<12>")
              (direction OUTPUT)
              (designator "51")
            )
            (port (rename row_11__ "row<11>")
              (direction OUTPUT)
              (designator "71")
            )
            (port (rename row_14__ "row<14>")
              (direction OUTPUT)
              (designator "76")
            )
            (port (rename row_1__ "row<1>")
              (direction OUTPUT)
              (designator "52")
            )
            (port (rename row_12__ "row<12>")
              (direction OUTPUT)
              (designator "70")
            )
            (port (rename col_11__ "col<11>")
              (direction OUTPUT)
              (designator "48")
            )
            (port (rename col_10__ "col<10>")
              (direction OUTPUT)
              (designator "47")
            )
            (port (rename row_2__ "row<2>")
              (direction OUTPUT)
              (designator "58")
            )
            (port (rename row_8__ "row<8>")
              (direction OUTPUT)
              (designator "66")
            )
            (port (rename row_15__ "row<15>")
              (direction OUTPUT)
              (designator "77")
            )
            (port (rename col_4__ "col<4>")
              (direction OUTPUT)
              (designator "26")
            )
            (port (rename col_6__ "col<6>")
              (direction OUTPUT)
              (designator "34")
            )
            (port (rename row_3__ "row<3>")
              (direction OUTPUT)
              (designator "61")
            )
            (port (rename row_4__ "row<4>")
              (direction OUTPUT)
              (designator "63")
            )