ex4.vm6

来自「[VHDL经典设计26例]--在xilinx芯片上调试通过--[01--1位全加」· VM6 代码 · 共 375 行 · 第 1/2 页

VM6
375 行
字号
12
NODE | N_A<2> | 534 | ? | 0 | 0 | EX4_COPY_0_COPY_0 | NULL | NULL | N_A<2> | 0 | 5 | II_IMUX
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | N_A<3> | 536 | ? | 0 | 0 | EX4_COPY_0_COPY_0 | NULL | NULL | N_A<3> | 0 | 5 | II_IMUX
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | N_A<0> | 537 | ? | 0 | 0 | EX4_COPY_0_COPY_0 | NULL | NULL | N_A<0> | 0 | 5 | II_IMUX
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | N_A<1> | 535 | ? | 0 | 0 | EX4_COPY_0_COPY_0 | NULL | NULL | N_A<1> | 0 | 5 | II_IMUX
OUTPUT_NODE_TYPE | 0 | 0 | MC_Q
NODE | C0/N52 | 542 | ? | 0 | 0 | EX4_COPY_0_COPY_0 | NULL | C0/N52.Q | C0/N52 | 0 | 0 | MC_Q
OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM
NODE | C0/N52.UIM | 588 | ? | 0 | 0 | EX4_COPY_0_COPY_0 | NULL | C0/N52.Q | C0/N52 | 1 | 0 | MC_UIM

SIGNAL_INSTANCE | C0/N52.SI | C0/N52 | 0 | 4 | 2
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | N_A<2> | 534 | ? | 0 | 0 | EX4_COPY_0_COPY_0 | NULL | NULL | N_A<2> | 0 | 5 | II_IMUX
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | N_A<3> | 536 | ? | 0 | 0 | EX4_COPY_0_COPY_0 | NULL | NULL | N_A<3> | 0 | 5 | II_IMUX
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | N_A<0> | 537 | ? | 0 | 0 | EX4_COPY_0_COPY_0 | NULL | NULL | N_A<0> | 0 | 5 | II_IMUX
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | N_A<1> | 535 | ? | 0 | 0 | EX4_COPY_0_COPY_0 | NULL | NULL | N_A<1> | 0 | 5 | II_IMUX
OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
SIGNAL | NODE | C0/N52.D1 | 573 | ? | 0 | 4096 | C0/N52 | NULL | NULL | C0/N52.SI | 1 | 9 | MC_SI_D1
SPPTERM | 0 | IV_ZERO
OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
SIGNAL | NODE | C0/N52.D2 | 574 | ? | 0 | 4096 | C0/N52 | NULL | NULL | C0/N52.SI | 2 | 9 | MC_SI_D2
SPPTERM | 3 | IV_FALSE | N_A<2> | IV_TRUE | N_A<1> | IV_FALSE | N_A<3>
SPPTERM | 3 | IV_FALSE | N_A<2> | IV_FALSE | N_A<3> | IV_TRUE | N_A<0>
SPPTERM | 3 | IV_TRUE | N_A<1> | IV_FALSE | N_A<3> | IV_TRUE | N_A<0>
SPPTERM | 4 | IV_TRUE | N_A<2> | IV_FALSE | N_A<1> | IV_TRUE | N_A<3> | IV_TRUE | N_A<0>

SRFF_INSTANCE | C0/N52.REG | C0/N52 | 0 | 1 | 1
INPUT_NODE_TYPE | 0 | 8 | SRFF_D
NODE | C0/N52.D | 572 | ? | 0 | 0 | C0/N52 | NULL | NULL | C0/N52.XOR | 0 | 7 | ALU_F
OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
NODE | C0/N52.Q | 575 | ? | 0 | 0 | C0/N52 | NULL | NULL | C0/N52.REG | 0 | 8 | SRFF_Q

MACROCELL_INSTANCE | Inv+OptxMapped | C0/N70 | EX4_COPY_0_COPY_0 | 2155872512 | 4 | 2
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | N_A<3> | 536 | ? | 0 | 0 | EX4_COPY_0_COPY_0 | NULL | NULL | N_A<3> | 0 | 5 | II_IMUX
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | N_A<0> | 537 | ? | 0 | 0 | EX4_COPY_0_COPY_0 | NULL | NULL | N_A<0> | 0 | 5 | II_IMUX
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | N_A<2> | 534 | ? | 0 | 0 | EX4_COPY_0_COPY_0 | NULL | NULL | N_A<2> | 0 | 5 | II_IMUX
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | N_A<1> | 535 | ? | 0 | 0 | EX4_COPY_0_COPY_0 | NULL | NULL | N_A<1> | 0 | 5 | II_IMUX
OUTPUT_NODE_TYPE | 0 | 0 | MC_Q
NODE | C0/N70 | 543 | ? | 0 | 0 | EX4_COPY_0_COPY_0 | NULL | C0/N70.Q | C0/N70 | 0 | 0 | MC_Q
OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM
NODE | C0/N70.UIM | 589 | ? | 0 | 0 | EX4_COPY_0_COPY_0 | NULL | C0/N70.Q | C0/N70 | 1 | 0 | MC_UIM

SIGNAL_INSTANCE | C0/N70.SI | C0/N70 | 0 | 4 | 2
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | N_A<3> | 536 | ? | 0 | 0 | EX4_COPY_0_COPY_0 | NULL | NULL | N_A<3> | 0 | 5 | II_IMUX
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | N_A<0> | 537 | ? | 0 | 0 | EX4_COPY_0_COPY_0 | NULL | NULL | N_A<0> | 0 | 5 | II_IMUX
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | N_A<2> | 534 | ? | 0 | 0 | EX4_COPY_0_COPY_0 | NULL | NULL | N_A<2> | 0 | 5 | II_IMUX
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | N_A<1> | 535 | ? | 0 | 0 | EX4_COPY_0_COPY_0 | NULL | NULL | N_A<1> | 0 | 5 | II_IMUX
OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
SIGNAL | NODE | C0/N70.D1 | 577 | ? | 0 | 4096 | C0/N70 | NULL | NULL | C0/N70.SI | 1 | 9 | MC_SI_D1
SPPTERM | 0 | IV_ZERO
OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
SIGNAL | NODE | C0/N70.D2 | 578 | ? | 0 | 4096 | C0/N70 | NULL | NULL | C0/N70.SI | 2 | 9 | MC_SI_D2
SPPTERM | 2 | IV_FALSE | N_A<3> | IV_TRUE | N_A<0>
SPPTERM | 3 | IV_TRUE | N_A<2> | IV_FALSE | N_A<1> | IV_FALSE | N_A<3>
SPPTERM | 3 | IV_FALSE | N_A<2> | IV_FALSE | N_A<1> | IV_TRUE | N_A<0>

SRFF_INSTANCE | C0/N70.REG | C0/N70 | 0 | 1 | 1
INPUT_NODE_TYPE | 0 | 8 | SRFF_D
NODE | C0/N70.D | 576 | ? | 0 | 0 | C0/N70 | NULL | NULL | C0/N70.XOR | 0 | 7 | ALU_F
OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
NODE | C0/N70.Q | 579 | ? | 0 | 0 | C0/N70 | NULL | NULL | C0/N70.REG | 0 | 8 | SRFF_Q

MACROCELL_INSTANCE | Inv+OptxMapped | C0/N88 | EX4_COPY_0_COPY_0 | 2155872512 | 4 | 2
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | N_A<2> | 534 | ? | 0 | 0 | EX4_COPY_0_COPY_0 | NULL | NULL | N_A<2> | 0 | 5 | II_IMUX
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | N_A<1> | 535 | ? | 0 | 0 | EX4_COPY_0_COPY_0 | NULL | NULL | N_A<1> | 0 | 5 | II_IMUX
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | N_A<0> | 537 | ? | 0 | 0 | EX4_COPY_0_COPY_0 | NULL | NULL | N_A<0> | 0 | 5 | II_IMUX
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | N_A<3> | 536 | ? | 0 | 0 | EX4_COPY_0_COPY_0 | NULL | NULL | N_A<3> | 0 | 5 | II_IMUX
OUTPUT_NODE_TYPE | 0 | 0 | MC_Q
NODE | C0/N88 | 544 | ? | 0 | 0 | EX4_COPY_0_COPY_0 | NULL | C0/N88.Q | C0/N88 | 0 | 0 | MC_Q
OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM
NODE | C0/N88.UIM | 590 | ? | 0 | 0 | EX4_COPY_0_COPY_0 | NULL | C0/N88.Q | C0/N88 | 1 | 0 | MC_UIM

SIGNAL_INSTANCE | C0/N88.SI | C0/N88 | 0 | 4 | 2
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | N_A<2> | 534 | ? | 0 | 0 | EX4_COPY_0_COPY_0 | NULL | NULL | N_A<2> | 0 | 5 | II_IMUX
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | N_A<1> | 535 | ? | 0 | 0 | EX4_COPY_0_COPY_0 | NULL | NULL | N_A<1> | 0 | 5 | II_IMUX
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | N_A<0> | 537 | ? | 0 | 0 | EX4_COPY_0_COPY_0 | NULL | NULL | N_A<0> | 0 | 5 | II_IMUX
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | N_A<3> | 536 | ? | 0 | 0 | EX4_COPY_0_COPY_0 | NULL | NULL | N_A<3> | 0 | 5 | II_IMUX
OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
SIGNAL | NODE | C0/N88.D1 | 581 | ? | 0 | 4096 | C0/N88 | NULL | NULL | C0/N88.SI | 1 | 9 | MC_SI_D1
SPPTERM | 0 | IV_ZERO
OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
SIGNAL | NODE | C0/N88.D2 | 582 | ? | 0 | 4096 | C0/N88 | NULL | NULL | C0/N88.SI | 2 | 9 | MC_SI_D2
SPPTERM | 3 | IV_TRUE | N_A<2> | IV_TRUE | N_A<1> | IV_TRUE | N_A<0>
SPPTERM | 4 | IV_TRUE | N_A<2> | IV_FALSE | N_A<1> | IV_FALSE | N_A<3> | IV_FALSE | N_A<0>
SPPTERM | 4 | IV_FALSE | N_A<2> | IV_TRUE | N_A<1> | IV_TRUE | N_A<3> | IV_FALSE | N_A<0>
SPPTERM | 4 | IV_FALSE | N_A<2> | IV_FALSE | N_A<1> | IV_FALSE | N_A<3> | IV_TRUE | N_A<0>

SRFF_INSTANCE | C0/N88.REG | C0/N88 | 0 | 1 | 1
INPUT_NODE_TYPE | 0 | 8 | SRFF_D
NODE | C0/N88.D | 580 | ? | 0 | 0 | C0/N88 | NULL | NULL | C0/N88.XOR | 0 | 7 | ALU_F
OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
NODE | C0/N88.Q | 583 | ? | 0 | 0 | C0/N88 | NULL | NULL | C0/N88.REG | 0 | 8 | SRFF_Q

OUTPUT_INSTANCE | 0 | LED7S<2> | EX4_COPY_0_COPY_0 | 3 | 1 | 1
INPUT_NODE_TYPE | 0 | 6 | OI_IN
NODE | C0/N106 | 538 | ? | 0 | 0 | EX4_COPY_0_COPY_0 | NULL | C0/N106.Q | C0/N106 | 0 | 0 | MC_Q
OUTPUT_NODE_TYPE | 0 | 6 | OI_OUT
NODE | LED7S<2> | 545 | PO | 0 | 0 | EX4_COPY_0_COPY_0 | NULL | NULL | LED7S<2> | 0 | 6 | OI_OUT

OUTPUT_INSTANCE | 0 | LED7S<1> | EX4_COPY_0_COPY_0 | 3 | 1 | 1
INPUT_NODE_TYPE | 0 | 6 | OI_IN
NODE | C0/N124 | 539 | ? | 0 | 0 | EX4_COPY_0_COPY_0 | NULL | C0/N124.Q | C0/N124 | 0 | 0 | MC_Q
OUTPUT_NODE_TYPE | 0 | 6 | OI_OUT
NODE | LED7S<1> | 546 | PO | 0 | 0 | EX4_COPY_0_COPY_0 | NULL | NULL | LED7S<1> | 0 | 6 | OI_OUT

OUTPUT_INSTANCE | 0 | LED7S<0> | EX4_COPY_0_COPY_0 | 3 | 1 | 1
INPUT_NODE_TYPE | 0 | 6 | OI_IN
NODE | C0/N142 | 540 | ? | 0 | 0 | EX4_COPY_0_COPY_0 | NULL | C0/N142.Q | C0/N142 | 0 | 0 | MC_Q
OUTPUT_NODE_TYPE | 0 | 6 | OI_OUT
NODE | LED7S<0> | 547 | PO | 0 | 0 | EX4_COPY_0_COPY_0 | NULL | NULL | LED7S<0> | 0 | 6 | OI_OUT

OUTPUT_INSTANCE | 0 | LED7S<6> | EX4_COPY_0_COPY_0 | 3 | 1 | 1
INPUT_NODE_TYPE | 0 | 6 | OI_IN
NODE | C0/N34 | 541 | ? | 0 | 0 | EX4_COPY_0_COPY_0 | NULL | C0/N34.Q | C0/N34 | 0 | 0 | MC_Q
OUTPUT_NODE_TYPE | 0 | 6 | OI_OUT
NODE | LED7S<6> | 548 | PO | 0 | 0 | EX4_COPY_0_COPY_0 | NULL | NULL | LED7S<6> | 0 | 6 | OI_OUT

OUTPUT_INSTANCE | 0 | LED7S<5> | EX4_COPY_0_COPY_0 | 3 | 1 | 1
INPUT_NODE_TYPE | 0 | 6 | OI_IN
NODE | C0/N52 | 542 | ? | 0 | 0 | EX4_COPY_0_COPY_0 | NULL | C0/N52.Q | C0/N52 | 0 | 0 | MC_Q
OUTPUT_NODE_TYPE | 0 | 6 | OI_OUT
NODE | LED7S<5> | 549 | PO | 0 | 0 | EX4_COPY_0_COPY_0 | NULL | NULL | LED7S<5> | 0 | 6 | OI_OUT

OUTPUT_INSTANCE | 0 | LED7S<4> | EX4_COPY_0_COPY_0 | 3 | 1 | 1
INPUT_NODE_TYPE | 0 | 6 | OI_IN
NODE | C0/N70 | 543 | ? | 0 | 0 | EX4_COPY_0_COPY_0 | NULL | C0/N70.Q | C0/N70 | 0 | 0 | MC_Q
OUTPUT_NODE_TYPE | 0 | 6 | OI_OUT
NODE | LED7S<4> | 550 | PO | 0 | 0 | EX4_COPY_0_COPY_0 | NULL | NULL | LED7S<4> | 0 | 6 | OI_OUT

OUTPUT_INSTANCE | 0 | LED7S<3> | EX4_COPY_0_COPY_0 | 3 | 1 | 1
INPUT_NODE_TYPE | 0 | 6 | OI_IN
NODE | C0/N88 | 544 | ? | 0 | 0 | EX4_COPY_0_COPY_0 | NULL | C0/N88.Q | C0/N88 | 0 | 0 | MC_Q
OUTPUT_NODE_TYPE | 0 | 6 | OI_OUT
NODE | LED7S<3> | 551 | PO | 0 | 0 | EX4_COPY_0_COPY_0 | NULL | NULL | LED7S<3> | 0 | 6 | OI_OUT

FB_INSTANCE | FOOBAR1_ | EX4_COPY_0_COPY_0 | 0 | 0 | 0
FBPIN | 13 | NULL | 0 | N_A<0> | 0 | NULL | 0 | 20 | 49152
FBPIN | 16 | NULL | 0 | N_A<1> | 0 | NULL | 0 | 23 | 49152
FBPIN | 18 | NULL | 0 | N_A<2> | 0 | NULL | 0 | 24 | 49152

FB_INSTANCE | FOOBAR2_ | EX4_COPY_0_COPY_0 | 0 | 0 | 0
FBPIN | 2 | C0/N124 | 1 | NULL | 0 | LED7S<1> | 1 | 69 | 49152
FBPIN | 4 | C0/N106 | 1 | NULL | 0 | LED7S<2> | 1 | 68 | 49152
FBPIN | 5 | C0/N70 | 1 | NULL | 0 | LED7S<4> | 1 | 70 | 49152
FBPIN | 6 | C0/N88 | 1 | NULL | 0 | LED7S<3> | 1 | 71 | 49152
FBPIN | 7 | C0/N34 | 1 | NULL | 0 | LED7S<6> | 1 | 76 | 53248
FBPIN | 8 | C0/N52 | 1 | NULL | 0 | LED7S<5> | 1 | 72 | 49152

FB_INSTANCE | FOOBAR3_ | EX4_COPY_0_COPY_0 | 0 | 0 | 0
FBPIN | 1 | NULL | 0 | N_A<3> | 0 | NULL | 0 | 25 | 49152

FB_INSTANCE | FOOBAR4_ | EX4_COPY_0_COPY_0 | 0 | 0 | 0
FBPIN | 17 | C0/N142 | 1 | NULL | 0 | LED7S<0> | 1 | 66 | 49152

FB_INSTANCE | INPUTPINS_FOOBAR5_ | EX4_COPY_0_COPY_0 | 0 | 0 | 0

FB_ORDER_OF_INPUTS | FOOBAR2_ | 6 | A<1> | 23 | 12 | A<3> | 25 | 14 | A<2> | 24 | 16 | A<0> | 20

FB_IMUX_INDEX | FOOBAR2_ | -1 | -1 | -1 | -1 | -1 | -1 | 132 | -1 | -1 | -1 | -1 | -1 | 138 | -1 | 140 | -1 | 123 | -1 | -1 | -1 | -1 | -1 | -1 | -1 | -1 | -1 | -1 | -1 | -1 | -1 | -1 | -1 | -1 | -1 | -1 | -1


FB_ORDER_OF_INPUTS | FOOBAR4_ | 13 | A<1> | 23 | 22 | A<3> | 25 | 25 | A<2> | 24 | 35 | A<0> | 20

FB_IMUX_INDEX | FOOBAR4_ | -1 | -1 | -1 | -1 | -1 | -1 | -1 | -1 | -1 | -1 | -1 | -1 | -1 | 132 | -1 | -1 | -1 | -1 | -1 | -1 | -1 | -1 | 138 | -1 | -1 | 140 | -1 | -1 | -1 | -1 | -1 | -1 | -1 | -1 | -1 | 123
12

ex4.vm6 - 源码说明

本页面展示了「[VHDL经典设计26例]--在xilinx芯片上调试通过--[01--1位全加器][02--2选1多路选择器][03--8位硬件加法器][04--7段数码显示译码器][05--8位串入并出寄存器][」中的 ex4.vm6 源码文件，采用 VM6 编程语言编写，共 375 行代码。您可以在线阅读完整代码内容，也可以返回资源详情页下载完整源码包进行本地学习和开发。

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