ex4.tim

来自「[VHDL经典设计26例]--在xilinx芯片上调试通过--[01--1位全加」· TIM 代码 · 共 61 行

                           Performance Summary Report
                           --------------------------

Design:     ex4
Device:     XC9572-7-PC84
Speed File: Version 3.0
Program:    Timing Report Generator:  version E.38
Date:       Tue Mar 11 23:08:42 2008

Performance Summary: 

Pad to Pad (tPD)                          :          7.5ns (1 macrocell levels)
Pad 'A<2>' to Pad 'LED7S<2>'                                      

--------------------------------------------------------------------------------
                            Pad to Pad (tPD) (nsec)

\ From       A     A     A     A
 \           <     <     <     <
  \          0     1     2     3
   \         >     >     >     >
    \                           
     \                          
      \                         
       \                        
  To    \------------------------

LED7S<0>   7.5   7.5   7.5   7.5
LED7S<1>   7.5   7.5   7.5   7.5
LED7S<2>   7.5   7.5   7.5   7.5
LED7S<3>   7.5   7.5   7.5   7.5
LED7S<4>   7.5   7.5   7.5   7.5
LED7S<5>   7.5   7.5   7.5   7.5
LED7S<6>   7.5   7.5   7.5   7.5

Path Type Definition: 

Pad to Pad (tPD) -                        Reports pad to pad paths that start 
                                          at input pads and end at output pads. 
                                          Paths are not traced through 
                                          registers. 

Clock Pad to Output Pad (tCO) -           Reports paths that start at input 
                                          pads trace through clock inputs of 
                                          registers and end at output pads. 
                                          Paths are not traced through PRE/CLR 
                                          inputs of registers. 

Setup to Clock at Pad (tSU) -             Reports external setup time of data 
                                          to clock at pad. Data path starts at 
                                          an input pad and end at register D/T 
                                          input. Clock path starts at input pad 
                                          and ends at the register clock input. 
                                          Paths are not traced through 
                                          registers. 

Clock to Setup (tCYC) -                   Register to register cycle time. 
                                          Include source register tCO and 
                                          destination register tSU.