ex4.bld

[VHDL经典设计26例]--在xilinx芯片上调试通过--[01--1位全加器][02--2选1多路选择器][03--8位硬件加法器][04--7段数码显示译码器][05--8位串入并出寄存器][

Release FPGA Express Synthesis 3.7 - ngdbuild E.38
Copyright (c) 1995-2001 Xilinx, Inc.  All rights reserved.

Command Line: ngdbuild -p xc9500 -uc ex4.ucf -dd ..
D:\TEMP\EDA6000\XC95\EX4\ex4.edf ex4.ngd 

Launcher: Executing edif2ngd "D:\TEMP\EDA6000\XC95\EX4\ex4.edf"
"d:\temp\eda6000\xc95\ex4\xproj\ver1\ex4.ngo"
INFO:NgdBuild - Release FPGA Express Synthesis 3.7 - edif2ngd E.38
INFO:NgdBuild - Copyright (c) 1995-2001 Xilinx, Inc.  All rights reserved.
Writing the design to "d:/temp/eda6000/xc95/ex4/xproj/ver1/ex4.ngo"...
Reading NGO file "d:/temp/eda6000/xc95/ex4/xproj/ver1/ex4.ngo" ...
Reading component libraries for design expansion...

Annotating constraints to design from file "ex4.ucf" ...

Checking timing specifications ...
Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Writing NGD file "ex4.ngd" ...

Writing NGDBUILD log file "ex4.bld"...