ex2.rpt

来自「[VHDL经典设计26例]--在xilinx芯片上调试通过--[01--1位全加」· RPT 代码 · 共 42 行

 
cpldfit                             :  version E.38 Xilinx Inc.
                                  Fitter Report
Design Name: ex2                                 Date:  3-11-2008,  1:32PM
Device Used: XC95108-10-PQ160
Fitting Status: Did NOT Fit

****************************  Errors and Warnings  *************************

ERROR:Cpld:828 - 'a' is assigned to an invalid location ('P20') for this device.
    This will prevent the design from fitting on the current device. 'a' must be
   reassigned before attempting a re-fit.
ERROR:Cpld:864 - Cannot fit the design into any of the specified devices with
   the selected implementation options.
****************************  Compiler Options  ****************************

Following is a list of all global compiler options used by the fitter run.

Device(s) Specified                         : XC95108-10-PQ160
Use Timing Constraints                      : ON
Use Design Location Constraints             : ON
Create Programmable Ground Pins             : OFF
Use Advanced Fitting                        : ON
Use Local Feedback                          : ON
Use Pin Feedback                            : ON
Default Power Setting                       : STD
Default Output Slew Rate                    : FAST
Guide File Used                             : NONE
Multi Level Logic Optimization              : ON
Timing Optimization                         : ON
Power/Slew Optimization                     : OFF
High Fitting Effort                         : ON
Automatic Wire-ANDing                       : ON
Xor Synthesis                               : ON
D/T Synthesis                               : ON
Use Boolean Minimization                    : ON
Global Clock(GCK) Optimization              : ON
Global Set/Reset(GSR) Optimization          : ON
Global Output Enable(GTS) Optimization      : ON
Collapsing pterm limit                      : 25
Collapsing input limit                      : 36