time_sim.edn
来自「[VHDL经典设计26例]--在xilinx芯片上调试通过--[01--1位全加」· EDN 代码 · 共 357 行
EDN
357 行
(edif ex2 (edifVersion 2 0 0) (edifLevel 0) (keywordMap (keywordLevel 0)) (status (written (timestamp 2008 3 11 12 47 4) (program "Xilinx ngd2edif" (version "E.38")) (comment "Command line: -w -v fndtn ex2.nga time_sim.edn "))) (external SIMPRIMS (edifLevel 0) (technology (numberDefinition (scale 1 (E 1 -12) (unit TIME)))) (cell x_opad (cellType GENERIC) (view view_1 (viewType NETLIST) (interface (port PAD (direction OUTPUT) ) ) ) ) (cell x_buf (cellType GENERIC) (view view_1 (viewType NETLIST) (interface (port IN (direction INPUT) ) (port OUT (direction OUTPUT) ) ) ) ) (cell x_zero (cellType GENERIC) (view view_1 (viewType NETLIST) (interface (port OUT (direction OUTPUT) ) ) ) ) (cell x_or2 (cellType GENERIC) (view view_1 (viewType NETLIST) (interface (port IN0 (direction INPUT) ) (port IN1 (direction INPUT) ) (port OUT (direction OUTPUT) ) ) ) ) (cell x_and2 (cellType GENERIC) (view view_1 (viewType NETLIST) (interface (port IN0 (direction INPUT) ) (port IN1 (direction INPUT) ) (port OUT (direction OUTPUT) ) ) ) ) (cell x_xor2 (cellType GENERIC) (view view_1 (viewType NETLIST) (interface (port IN0 (direction INPUT) ) (port IN1 (direction INPUT) ) (port OUT (direction OUTPUT) ) ) ) ) (cell x_ipad (cellType GENERIC) (view view_1 (viewType NETLIST) (interface (port PAD (direction INPUT) ) ) ) ) (cell x_inv (cellType GENERIC) (view view_1 (viewType NETLIST) (interface (port IN (direction INPUT) ) (port OUT (direction OUTPUT) ) ) ) ) ) (library ex2_lib (edifLevel 0) (technology (numberDefinition (scale 1 (E 1 -12) (unit TIME)))) (cell ex2 (cellType GENERIC) (view view_1 (viewType NETLIST) (interface (port a (direction INPUT) (designator "20") ) (port s (direction INPUT) (designator "24") ) (port b (direction INPUT) (designator "23") ) (port y (direction OUTPUT) (designator "56") ) (designator "XC95108-7-PC84") ) (contents (instance y_PAD (viewRef view_1 (cellRef x_opad (libraryRef SIMPRIMS))) ) (instance y_0 (viewRef view_1 (cellRef x_buf (libraryRef SIMPRIMS))) (portInstance OUT (property RISE (integer 2500) (unit TIME) (owner "Xilinx")) (property FALL (integer 2500) (unit TIME) (owner "Xilinx")) ) ) (instance C0_N6_1 (viewRef view_1 (cellRef x_buf (libraryRef SIMPRIMS))) ) (instance C0_N6_REG (viewRef view_1 (cellRef x_buf (libraryRef SIMPRIMS))) (portInstance OUT (property RISE (integer 500) (unit TIME) (owner "Xilinx")) (property FALL (integer 500) (unit TIME) (owner "Xilinx")) ) ) (instance GND_ZERO (viewRef view_1 (cellRef x_zero (libraryRef SIMPRIMS))) ) (instance C0_N6_D1_2 (viewRef view_1 (cellRef x_or2 (libraryRef SIMPRIMS))) ) (instance C0_N6_D2_PT_0_3 (viewRef view_1 (cellRef x_and2 (libraryRef SIMPRIMS))) (portInstance IN0 (property RISE (integer 2000) (unit TIME) (owner "Xilinx")) (property FALL (integer 2000) (unit TIME) (owner "Xilinx")) ) (portInstance IN1 (property RISE (integer 2000) (unit TIME) (owner "Xilinx")) (property FALL (integer 2000) (unit TIME) (owner "Xilinx")) ) ) (instance C0_N6_D2_PT_1_4 (viewRef view_1 (cellRef x_and2 (libraryRef SIMPRIMS))) (portInstance IN0 (property RISE (integer 2000) (unit TIME) (owner "Xilinx")) (property FALL (integer 2000) (unit TIME) (owner "Xilinx")) ) (portInstance IN1 (property RISE (integer 2000) (unit TIME) (owner "Xilinx")) (property FALL (integer 2000) (unit TIME) (owner "Xilinx")) ) ) (instance C0_N6_D2_5 (viewRef view_1 (cellRef x_or2 (libraryRef SIMPRIMS))) ) (instance C0_N6_XOR (viewRef view_1 (cellRef x_xor2 (libraryRef SIMPRIMS))) ) (instance a_PAD (viewRef view_1 (cellRef x_ipad (libraryRef SIMPRIMS))) ) (instance N_a_6 (viewRef view_1 (cellRef x_buf (libraryRef SIMPRIMS))) (portInstance OUT (property RISE (integer 2500) (unit TIME) (owner "Xilinx")) (property FALL (integer 2500) (unit TIME) (owner "Xilinx")) ) ) (instance s_PAD (viewRef view_1 (cellRef x_ipad (libraryRef SIMPRIMS))) ) (instance N_s_7 (viewRef view_1 (cellRef x_buf (libraryRef SIMPRIMS))) (portInstance OUT (property RISE (integer 2500) (unit TIME) (owner "Xilinx")) (property FALL (integer 2500) (unit TIME) (owner "Xilinx")) ) ) (instance b_PAD (viewRef view_1 (cellRef x_ipad (libraryRef SIMPRIMS))) ) (instance N_b_8 (viewRef view_1 (cellRef x_buf (libraryRef SIMPRIMS))) (portInstance OUT (property RISE (integer 2500) (unit TIME) (owner "Xilinx")) (property FALL (integer 2500) (unit TIME) (owner "Xilinx")) ) ) (instance NlwInverterBlock_C0_N6_D2_PT_0_IN1 (viewRef view_1 (cellRef x_inv (libraryRef SIMPRIMS))) ) (net a (joined (portRef a) (portRef PAD (instanceRef a_PAD)) (portRef IN (instanceRef N_a_6)) ) ) (net s (joined (portRef s) (portRef PAD (instanceRef s_PAD)) (portRef IN (instanceRef N_s_7)) ) ) (net b (joined (portRef b) (portRef PAD (instanceRef b_PAD)) (portRef IN (instanceRef N_b_8)) ) ) (net y (joined (portRef y) (portRef PAD (instanceRef y_PAD)) (portRef OUT (instanceRef y_0)) ) ) (net C0_N6 (joined (portRef IN (instanceRef y_0)) (portRef OUT (instanceRef C0_N6_1)) ) ) (net C0_N6_Q (joined (portRef IN (instanceRef C0_N6_1)) (portRef OUT (instanceRef C0_N6_REG)) ) ) (net C0_N6_D (joined (portRef IN (instanceRef C0_N6_REG)) (portRef OUT (instanceRef C0_N6_XOR)) ) ) (net C0_N6_D1 (joined (portRef OUT (instanceRef C0_N6_D1_2)) (portRef IN0 (instanceRef C0_N6_XOR)) ) ) (net N_a (joined (portRef IN0 (instanceRef C0_N6_D2_PT_0_3)) (portRef OUT (instanceRef N_a_6)) ) ) (net N_s (joined (portRef IN0 (instanceRef C0_N6_D2_PT_1_4)) (portRef OUT (instanceRef N_s_7)) (portRef IN (instanceRef NlwInverterBlock_C0_N6_D2_PT_0_IN1)) ) ) (net C0_N6_D2_PT_0 (joined (portRef OUT (instanceRef C0_N6_D2_PT_0_3)) (portRef IN0 (instanceRef C0_N6_D2_5)) ) ) (net N_b (joined (portRef IN1 (instanceRef C0_N6_D2_PT_1_4)) (portRef OUT (instanceRef N_b_8)) ) ) (net C0_N6_D2_PT_1 (joined (portRef OUT (instanceRef C0_N6_D2_PT_1_4)) (portRef IN1 (instanceRef C0_N6_D2_5)) ) ) (net C0_N6_D2 (joined (portRef OUT (instanceRef C0_N6_D2_5)) (portRef IN1 (instanceRef C0_N6_XOR)) ) ) (net GND (joined (portRef OUT (instanceRef GND_ZERO)) (portRef IN0 (instanceRef C0_N6_D1_2)) (portRef IN1 (instanceRef C0_N6_D1_2)) ) ) (net NlwInverterSignal_C0_N6_D2_PT_0_IN1 (joined (portRef OUT (instanceRef NlwInverterBlock_C0_N6_D2_PT_0_IN1)) (portRef IN1 (instanceRef C0_N6_D2_PT_0_3)) ) ) ) ) ) ) (design ex2 (cellRef ex2 (libraryRef ex2_lib) ) ))
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