ex2.mod

来自「[VHDL经典设计26例]--在xilinx芯片上调试通过--[01--1位全加」· MOD 代码 · 共 19 行

MODEL
MODEL_VERSION "v1998.8";
DESIGN "ex2";

/* port names and type */
INPUT S:PIN20 = a;
INPUT S:PIN24 = s;
INPUT S:PIN23 = b;
OUTPUT S:PIN56 = y;

/* timing arc definitions */
a_y_delay: DELAY a y;
s_y_delay: DELAY s y;
b_y_delay: DELAY b y;

/* timing check arc definitions */

ENDMODEL