ex3.vm6

来自「[VHDL经典设计26例]--在xilinx芯片上调试通过--[01--1位全加」· VM6 代码 · 共 927 行 · 第 1/5 页

VM6
927 行
字号
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SPPTERM | 4 | IV_TRUE | N_b<3> | IV_TRUE | N_a<3> | IV_TRUE | N_a<4>$X0$N_b<4>/N_a<4>$X0$N_b<4>_D.FBK | IV_TRUE | N_a<5>$X0$N_b<5>/N_a<5>$X0$N_b<5>_D.FBK

SRFF_INSTANCE | N_a<5>$X0$N_b<5>/N_a<5>$X0$N_b<5>_D.REG | N_a<5>$X0$N_b<5>/N_a<5>$X0$N_b<5>_D | 0 | 1 | 1
INPUT_NODE_TYPE | 0 | 8 | SRFF_D
NODE | N_a<5>$X0$N_b<5>/N_a<5>$X0$N_b<5>_D.D | 718 | ? | 0 | 0 | N_a<5>$X0$N_b<5>/N_a<5>$X0$N_b<5>_D | NULL | NULL | N_a<5>$X0$N_b<5>/N_a<5>$X0$N_b<5>_D.XOR | 0 | 7 | ALU_F
OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
NODE | N_a<5>$X0$N_b<5>/N_a<5>$X0$N_b<5>_D.Q | 721 | ? | 0 | 0 | N_a<5>$X0$N_b<5>/N_a<5>$X0$N_b<5>_D | NULL | NULL | N_a<5>$X0$N_b<5>/N_a<5>$X0$N_b<5>_D.REG | 0 | 8 | SRFF_Q

MACROCELL_INSTANCE | SoftPfbk+ClkInv | N_a<6>$X0$N_b<6>/N_a<6>$X0$N_b<6>_D | EX3_COPY_0_COPY_0 | 2248146944 | 2 | 2
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | N_b<6> | 633 | ? | 0 | 0 | EX3_COPY_0_COPY_0 | NULL | NULL | N_b<6> | 0 | 5 | II_IMUX
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | N_a<6> | 638 | ? | 0 | 0 | EX3_COPY_0_COPY_0 | NULL | NULL | N_a<6> | 0 | 5 | II_IMUX
OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM
NODE | N_a<6>$X0$N_b<6>/N_a<6>$X0$N_b<6>_D.UIM | 660 | ? | 0 | 0 | EX3_COPY_0_COPY_0 | NULL | N_a<6>$X0$N_b<6>/N_a<6>$X0$N_b<6>_D.Q | N_a<6>$X0$N_b<6>/N_a<6>$X0$N_b<6>_D | 1 | 0 | MC_UIM
OUTPUT_NODE_TYPE | 5 | 0 | MC_FBK
NODE | N_a<6>$X0$N_b<6>/N_a<6>$X0$N_b<6>_D.FBK | 781 | ? | 0 | 0 | EX3_COPY_0_COPY_0 | NULL | N_a<6>$X0$N_b<6>/N_a<6>$X0$N_b<6>_D.Q | N_a<6>$X0$N_b<6>/N_a<6>$X0$N_b<6>_D | 5 | 0 | MC_FBK

SIGNAL_INSTANCE | N_a<6>$X0$N_b<6>/N_a<6>$X0$N_b<6>_D.SI | N_a<6>$X0$N_b<6>/N_a<6>$X0$N_b<6>_D | 0 | 2 | 2
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | N_b<6> | 633 | ? | 0 | 0 | EX3_COPY_0_COPY_0 | NULL | NULL | N_b<6> | 0 | 5 | II_IMUX
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | N_a<6> | 638 | ? | 0 | 0 | EX3_COPY_0_COPY_0 | NULL | NULL | N_a<6> | 0 | 5 | II_IMUX
OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
SIGNAL | NODE | N_a<6>$X0$N_b<6>/N_a<6>$X0$N_b<6>_D.D1 | 723 | ? | 0 | 4096 | N_a<6>$X0$N_b<6>/N_a<6>$X0$N_b<6>_D | NULL | NULL | N_a<6>$X0$N_b<6>/N_a<6>$X0$N_b<6>_D.SI | 1 | 9 | MC_SI_D1
SPPTERM | 1 | IV_TRUE | N_b<6>
OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
SIGNAL | NODE | N_a<6>$X0$N_b<6>/N_a<6>$X0$N_b<6>_D.D2 | 724 | ? | 0 | 4096 | N_a<6>$X0$N_b<6>/N_a<6>$X0$N_b<6>_D | NULL | NULL | N_a<6>$X0$N_b<6>/N_a<6>$X0$N_b<6>_D.SI | 2 | 9 | MC_SI_D2
SPPTERM | 1 | IV_TRUE | N_a<6>

SRFF_INSTANCE | N_a<6>$X0$N_b<6>/N_a<6>$X0$N_b<6>_D.REG | N_a<6>$X0$N_b<6>/N_a<6>$X0$N_b<6>_D | 0 | 1 | 1
INPUT_NODE_TYPE | 0 | 8 | SRFF_D
NODE | N_a<6>$X0$N_b<6>/N_a<6>$X0$N_b<6>_D.D | 722 | ? | 0 | 0 | N_a<6>$X0$N_b<6>/N_a<6>$X0$N_b<6>_D | NULL | NULL | N_a<6>$X0$N_b<6>/N_a<6>$X0$N_b<6>_D.XOR | 0 | 7 | ALU_F
OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
NODE | N_a<6>$X0$N_b<6>/N_a<6>$X0$N_b<6>_D.Q | 725 | ? | 0 | 0 | N_a<6>$X0$N_b<6>/N_a<6>$X0$N_b<6>_D | NULL | NULL | N_a<6>$X0$N_b<6>/N_a<6>$X0$N_b<6>_D.REG | 0 | 8 | SRFF_Q

MACROCELL_INSTANCE | SoftPfbk+ClkInv | N_a<7>$X0$N_b<7>/N_a<7>$X0$N_b<7>_D | EX3_COPY_0_COPY_0 | 2248146944 | 8 | 3
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | N_b<7> | 640 | ? | 0 | 0 | EX3_COPY_0_COPY_0 | NULL | NULL | N_b<7> | 0 | 5 | II_IMUX
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | N_a<7> | 639 | ? | 0 | 0 | EX3_COPY_0_COPY_0 | NULL | NULL | N_a<7> | 0 | 5 | II_IMUX
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | N_a<6> | 638 | ? | 0 | 0 | EX3_COPY_0_COPY_0 | NULL | NULL | N_a<6> | 0 | 5 | II_IMUX
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | N_a<5>$X0$N_b<5>/N_a<5>$X0$N_b<5>_D.FBK | 780 | ? | 0 | 0 | EX3_COPY_0_COPY_0 | NULL | N_a<5>$X0$N_b<5>/N_a<5>$X0$N_b<5>_D.Q | N_a<5>$X0$N_b<5>/N_a<5>$X0$N_b<5>_D | 5 | 0 | MC_FBK
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | N_a<5> | 637 | ? | 0 | 0 | EX3_COPY_0_COPY_0 | NULL | NULL | N_a<5> | 0 | 5 | II_IMUX
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | N_a<4>$X0$N_b<4>/N_a<4>$X0$N_b<4>_D.FBK | 779 | ? | 0 | 0 | EX3_COPY_0_COPY_0 | NULL | N_a<4>$X0$N_b<4>/N_a<4>$X0$N_b<4>_D.Q | N_a<4>$X0$N_b<4>/N_a<4>$X0$N_b<4>_D | 5 | 0 | MC_FBK
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | N_a<4> | 636 | ? | 0 | 0 | EX3_COPY_0_COPY_0 | NULL | NULL | N_a<4> | 0 | 5 | II_IMUX
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | N_a<6>$X0$N_b<6>/N_a<6>$X0$N_b<6>_D.FBK | 781 | ? | 0 | 0 | EX3_COPY_0_COPY_0 | NULL | N_a<6>$X0$N_b<6>/N_a<6>$X0$N_b<6>_D.Q | N_a<6>$X0$N_b<6>/N_a<6>$X0$N_b<6>_D | 5 | 0 | MC_FBK
OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM
NODE | N_a<7>$X0$N_b<7>/N_a<7>$X0$N_b<7>_D.UIM | 661 | ? | 0 | 0 | EX3_COPY_0_COPY_0 | NULL | N_a<7>$X0$N_b<7>/N_a<7>$X0$N_b<7>_D.Q | N_a<7>$X0$N_b<7>/N_a<7>$X0$N_b<7>_D | 1 | 0 | MC_UIM
OUTPUT_NODE_TYPE | 4 | 0 | MC_EXPORT
NODE | N_a<7>$X0$N_b<7>/N_a<7>$X0$N_b<7>_D.EXP | 762 | ? | 0 | 0 | EX3_COPY_0_COPY_0 | NULL | N_a<7>$X0$N_b<7>/N_a<7>$X0$N_b<7>_D.EXP | N_a<7>$X0$N_b<7>/N_a<7>$X0$N_b<7>_D | 4 | 0 | MC_EXPORT
OUTPUT_NODE_TYPE | 5 | 0 | MC_FBK
NODE | N_a<7>$X0$N_b<7>/N_a<7>$X0$N_b<7>_D.FBK | 782 | ? | 0 | 0 | EX3_COPY_0_COPY_0 | NULL | N_a<7>$X0$N_b<7>/N_a<7>$X0$N_b<7>_D.Q | N_a<7>$X0$N_b<7>/N_a<7>$X0$N_b<7>_D | 5 | 0 | MC_FBK

SIGNAL_INSTANCE | N_a<7>$X0$N_b<7>/N_a<7>$X0$N_b<7>_D.SI | N_a<7>$X0$N_b<7>/N_a<7>$X0$N_b<7>_D | 0 | 8 | 3
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | N_b<7> | 640 | ? | 0 | 0 | EX3_COPY_0_COPY_0 | NULL | NULL | N_b<7> | 0 | 5 | II_IMUX
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | N_a<7> | 639 | ? | 0 | 0 | EX3_COPY_0_COPY_0 | NULL | NULL | N_a<7> | 0 | 5 | II_IMUX
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | N_a<6> | 638 | ? | 0 | 0 | EX3_COPY_0_COPY_0 | NULL | NULL | N_a<6> | 0 | 5 | II_IMUX
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | N_a<5>$X0$N_b<5>/N_a<5>$X0$N_b<5>_D.FBK | 780 | ? | 0 | 0 | EX3_COPY_0_COPY_0 | NULL | N_a<5>$X0$N_b<5>/N_a<5>$X0$N_b<5>_D.Q | N_a<5>$X0$N_b<5>/N_a<5>$X0$N_b<5>_D | 5 | 0 | MC_FBK
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | N_a<5> | 637 | ? | 0 | 0 | EX3_COPY_0_COPY_0 | NULL | NULL | N_a<5> | 0 | 5 | II_IMUX
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | N_a<4>$X0$N_b<4>/N_a<4>$X0$N_b<4>_D.FBK | 779 | ? | 0 | 0 | EX3_COPY_0_COPY_0 | NULL | N_a<4>$X0$N_b<4>/N_a<4>$X0$N_b<4>_D.Q | N_a<4>$X0$N_b<4>/N_a<4>$X0$N_b<4>_D | 5 | 0 | MC_FBK
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | N_a<4> | 636 | ? | 0 | 0 | EX3_COPY_0_COPY_0 | NULL | NULL | N_a<4> | 0 | 5 | II_IMUX
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | N_a<6>$X0$N_b<6>/N_a<6>$X0$N_b<6>_D.FBK | 781 | ? | 0 | 0 | EX3_COPY_0_COPY_0 | NULL | N_a<6>$X0$N_b<6>/N_a<6>$X0$N_b<6>_D.Q | N_a<6>$X0$N_b<6>/N_a<6>$X0$N_b<6>_D | 5 | 0 | MC_FBK
OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
SIGNAL | NODE | N_a<7>$X0$N_b<7>/N_a<7>$X0$N_b<7>_D.D1 | 727 | ? | 0 | 4096 | N_a<7>$X0$N_b<7>/N_a<7>$X0$N_b<7>_D | NULL | NULL | N_a<7>$X0$N_b<7>/N_a<7>$X0$N_b<7>_D.SI | 1 | 9 | MC_SI_D1
SPPTERM | 1 | IV_TRUE | N_b<7>
OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
SIGNAL | NODE | N_a<7>$X0$N_b<7>/N_a<7>$X0$N_b<7>_D.D2 | 728 | ? | 0 | 4096 | N_a<7>$X0$N_b<7>/N_a<7>$X0$N_b<7>_D | NULL | NULL | N_a<7>$X0$N_b<7>/N_a<7>$X0$N_b<7>_D.SI | 2 | 9 | MC_SI_D2
SPPTERM | 1 | IV_TRUE | N_a<7>
OUTPUT_NODE_TYPE | 7 | 9 | MC_SI_EXPORT
SIGNAL | NODE | N_a<7>$X0$N_b<7>/N_a<7>$X0$N_b<7>_D.EXP | 750 | ? | 0 | 0 | N_a<7>$X0$N_b<7>/N_a<7>$X0$N_b<7>_D | NULL | NULL | N_a<7>$X0$N_b<7>/N_a<7>$X0$N_b<7>_D.SI | 7 | 9 | MC_SI_EXPORT
SPPTERM | 2 | IV_TRUE | N_a<6> | IV_FALSE | N_a<6>$X0$N_b<6>/N_a<6>$X0$N_b<6>_D.FBK
SPPTERM | 3 | IV_TRUE | N_a<5> | IV_FALSE | N_a<5>$X0$N_b<5>/N_a<5>$X0$N_b<5>_D.FBK | IV_TRUE | N_a<6>$X0$N_b<6>/N_a<6>$X0$N_b<6>_D.FBK
SPPTERM | 4 | IV_TRUE | N_a<4> | IV_FALSE | N_a<4>$X0$N_b<4>/N_a<4>$X0$N_b<4>_D.FBK | IV_TRUE | N_a<5>$X0$N_b<5>/N_a<5>$X0$N_b<5>_D.FBK | IV_TRUE | N_a<6>$X0$N_b<6>/N_a<6>$X0$N_b<6>_D.FBK

SRFF_INSTANCE | N_a<7>$X0$N_b<7>/N_a<7>$X0$N_b<7>_D.REG | N_a<7>$X0$N_b<7>/N_a<7>$X0$N_b<7>_D | 0 | 1 | 1
INPUT_NODE_TYPE | 0 | 8 | SRFF_D
NODE | N_a<7>$X0$N_b<7>/N_a<7>$X0$N_b<7>_D.D | 726 | ? | 0 | 0 | N_a<7>$X0$N_b<7>/N_a<7>$X0$N_b<7>_D | NULL | NULL | N_a<7>$X0$N_b<7>/N_a<7>$X0$N_b<7>_D.XOR | 0 | 7 | ALU_F
OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
NODE | N_a<7>$X0$N_b<7>/N_a<7>$X0$N_b<7>_D.Q | 729 | ? | 0 | 0 | N_a<7>$X0$N_b<7>/N_a<7>$X0$N_b<7>_D | NULL | NULL | N_a<7>$X0$N_b<7>/N_a<7>$X0$N_b<7>_D.REG | 0 | 8 | SRFF_Q

MACROCELL_INSTANCE | OptxMapped | _8_ | EX3_COPY_0_COPY_0 | 2155872256 | 11 | 3
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | N_a<1> | 627 | ? | 0 | 0 | EX3_COPY_0_COPY_0 | NULL | NULL | N_a<1> | 0 | 5 | II_IMUX
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | N_b<1> | 628 | ? | 0 | 0 | EX3_COPY_0_COPY_0 | NULL | NULL | N_b<1> | 0 | 5 | II_IMUX
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | N_b<3> | 630 | ? | 0 | 0 | EX3_COPY_0_COPY_0 | NULL | NULL | N_b<3> | 0 | 5 | II_IMUX
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | N_a<2> | 634 | ? | 0 | 0 | EX3_COPY_0_COPY_0 | NULL | NULL | N_a<2> | 0 | 5 | II_IMUX
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | N_a<5>$X0$N_b<5>/N_a<5>$X0$N_b<5>_D.FBK | 780 | ? | 0 | 0 | EX3_COPY_0_COPY_0 | NULL | N_a<5>$X0$N_b<5>/N_a<5>$X0$N_b<5>_D.Q | N_a<5>$X0$N_b<5>/N_a<5>$X0$N_b<5>_D | 5 | 0 | MC_FBK
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | N_a<0> | 625 | ? | 0 | 0 | EX3_COPY_0_COPY_0 | NULL | NULL | N_a<0> | 0 | 5 | II_IMUX
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | N_b<0> | 626 | ? | 0 | 0 | EX3_COPY_0_COPY_0 | NULL | NULL | N_b<0> | 0 | 5 | II_IMUX
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | N_b<2> | 629 | ? | 0 | 0 | EX3_COPY_0_COPY_0 | NULL | NULL | N_b<2> | 0 | 5 | II_IMUX
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | N_a<3> | 635 | ? | 0 | 0 | EX3_COPY_0_COPY_0 | NULL | NULL | N_a<3> | 0 | 5 | II_IMUX
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | _9_.EXP | 758 | ? | 0 | 0 | EX3_COPY_0_COPY_0 | NULL | _9_.EXP | _9_ | 4 | 0 | MC_EXPORT
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | N_a<4>$X0$N_b<4>/N_a<4>$X0$N_b<4>_D.FBK | 779 | ? | 0 | 0 | EX3_COPY_0_COPY_0 | NULL | N_a<4>$X0$N_b<4>/N_a<4>$X0$N_b<4>_D.Q | N_a<4>$X0$N_b<4>/N_a<4>$X0$N_b<4>_D | 5 | 0 | MC_FBK
OUTPUT_NODE_TYPE | 0 | 0 | MC_Q
NODE | N45 | 735 | ? | 0 | 0 | EX3_COPY_0_COPY_0 | NULL | HPART_CREATED_0.Q | _8_ | 0 | 0 | MC_Q
OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM
NODE | _8_.UIM | 792 | ? | 0 | 0 | EX3_COPY_0_COPY_0 | NULL | HPART_CREATED_0.Q | _8_ | 1 | 0 | MC_UIM
OUTPUT_NODE_TYPE | 4 | 0 | MC_EXPORT
NODE | _8_.EXP | 759 | ? | 0 | 0 | EX3_COPY_0_COPY_0 | NULL | _8_.EXP | _8_ | 4 | 0 | MC_EXPORT

SIGNAL_INSTANCE | HPART_CREATED_0.SI | _8_ | 0 | 11 | 3
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | N_a<1> | 627 | ? | 0 | 0 | EX3_COPY_0_COPY_0 | NULL | NULL | N_a<1> | 0 | 5 | II_IMUX
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | N_b<1> | 628 | ? | 0 | 0 | EX3_COPY_0_COPY_0 | NULL | NULL | N_b<1> | 0 | 5 | II_IMUX
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | N_b<3> | 630 | ? | 0 | 0 | EX3_COPY_0_COPY_0 | NULL | NULL | N_b<3> | 0 | 5 | II_IMUX
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | N_a<2> | 634 | ? | 0 | 0 | EX3_COPY_0_COPY_0 | NULL | NULL | N_a<2> | 0 | 5 | II_IMUX
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | N_a<5>$X0$N_b<5>/N_a<5>$X0$N_b<5>_D.FBK | 780 | ? | 0 | 0 | EX3_COPY_0_COPY_0 | NULL | N_a<5>$X0$N_b<5>/N_a<5>$X0$N_b<5>_D.Q | N_a<5>$X0$N_b<5>/N_a<5>$X0$N_b<5>_D | 5 | 0 | MC_FBK
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | N_a<0> | 625 | ? | 0 | 0 | EX3_COPY_0_COPY_0 | NULL | NULL | N_a<0> | 0 | 5 | II_IMUX
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | N_b<0> | 626 | ? | 0 | 0 | EX3_COPY_0_COPY_0 | NULL | NULL | N_b<0> | 0 | 5 | II_IMUX
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | N_b<2> | 629 | ? | 0 | 0 | EX3_COPY_0_COPY_0 | NULL | NULL | N_b<2> | 0 | 5 | II_IMUX
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | N_a<3> | 635 | ? | 0 | 0 | EX3_COPY_0_COPY_0 | NULL | NULL | N_a<3> | 0 | 5 | II_IMUX
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | _9_.EXP | 758 | ? | 0 | 0 | EX3_COPY_0_COPY_0 | NULL | _9_.EXP | _9_ | 4 | 0 | MC_EXPORT
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | N_a<4>$X0$N_b<4>/N_a<4>$X0$N_b<4>_D.FBK | 779 | ? | 0 | 0 | EX3_COPY_0_COPY_0 | NULL | N_a<4>$X0$N_b<4>/N_a<4>$X0$N_b<4>_D.Q | N_a<4>$X0$N_b<4>/N_a<4>$X0$N_b<4>_D | 5 | 0 | MC_FBK
OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
SIGNAL | NODE | HPART_CREATED_0.D1 | 733 | ? | 0 | 0 | _8_ | NULL | NULL | HPART_CREATED_0.SI | 1 | 9 | MC_SI_D1
SPPTERM | 0 | IV_ZERO
OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
SIGNAL | NODE | HPART_CREATED_0.D2 | 732 | ? | 0 | 0 | _8_ | NULL | NULL | HPART_CREATED_0.SI | 2 | 9 | MC_SI_D2
SPPTERM | 1 | IV_TRUE | _9_.EXP
OUTPUT_NODE_TYPE | 7 | 9 | MC_SI_EXPORT
SIGNAL | NODE | _8_.EXP | 747 | ? | 0 | 0 | _8_ | NULL | NULL | HPART_CREATED_0.SI | 7 | 9 | MC_SI_EXPORT
SPPTERM | 6 | IV_TRUE | N_a<1> | IV_TRUE | N_b<1> | IV_TRUE | N_b<3> | IV_TRUE | N_a<2> | IV_TRUE | N_a<4>$X0$N_b<4>/N_a<4>$X0$N_b<4>_D.FBK | IV_TRUE | N_a<5>$X0$N_b<5>/N_a<5>$X0$N_b<5>_D.FBK
SPPTERM | 7 | IV_TRUE | N_a<0> | IV_TRUE | N_b<0> | IV_TRUE | N_a<1> | IV_TRUE | N_b<2> | IV_TRUE | N_a<3> | IV_TRUE | N_a<4>$X0$N_b<4>/N_a<4>$X0$N_b<4>_D.FBK | IV_TRUE | N_a<5>$X0$N_b<5>/N_a<5>$X0$N_b<5>_D.FBK
SPPTERM | 7 | IV_TRUE | N_a<0> | IV_TRUE | N_b<0> | IV_TRUE | N_a<1> | IV_TRUE | N_a<2> | IV_TRUE | N_a<3> | IV_TRUE | N_a<4>$X0$N_b<4>/N_a<4>$X0$N_b<4>_D.FBK | IV_TRUE | N_a<5>$X0$N_b<5>/N_a<5>$X0$N_b<5>_D.FBK
SPPTERM | 7 | IV_TRUE | N_a<0> | IV_TRUE | N_b<0> | IV_TRUE | N_b<1> | IV_TRUE | N_b<2> | IV_TRUE | N_a<3> | IV_TRUE | N_a<4>$X0$N_b<4>/N_a<4>$X0$N_b<4>_D.FBK | IV_TRUE | N_a<5>$X0$N_b<5>/N_a<5>$X0$N_b<5>_D.FBK
SPPTERM | 7 | IV_TRUE | N_a<0> | IV_TRUE | N_b<0> | IV_TRUE | N_b<1> | IV_TRUE | N_a<2> | IV_TRUE | N_a<3> | IV_TRUE | N_a<4>$X0$N_b<4>/N_a<4>$X0$N_b<4>_D.FBK | IV_TRUE | N_a<5>$X0$N_b<5>/N_a<5>$X0$N_b<5>_D.FBK

SRFF_INSTANCE | HPART_CREATED_0.REG | _8_ | 0 | 1 | 1
INPUT_NODE_TYPE | 0 | 8 | SRFF_D
NODE | HPART_CREATED_0.D | 731 | ? | 0 | 0 | _8_ | NULL | NULL | HPART_CREATED_0.XOR | 0 | 7 | ALU_F
OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
NODE | HPART_CREATED_0.Q | 734 | ? | 0 | 0 | _8_ | NULL | NULL | HPART_CREATED_0.REG | 0 | 8 | SRFF_Q

MACROCELL_INSTANCE | OptxMapped | _9_ | EX3_COPY_0_COPY_0 | 2155872256 | 2 | 3
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | sum<7>_BUFR.FBK | 784 | ? | 0 | 8 | EX3_COPY_0_COPY_0 | NULL | N45.Q | sum<7>_BUFR.MC | 5 | 0 | MC_FBK
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | sum<6>_BUFR.FBK | 783 | ? | 0 | 8 | EX3_COPY_0_COPY_0 | NULL | N44.Q | sum<6>_BUFR.MC | 5 | 0 | MC_FBK
OUTPUT_NODE_TYPE | 0 | 0 | MC_Q
NODE | N44 | 741 | ? | 0 | 0 | EX3_COPY_0_COPY_0 | NULL | HPART_CREATED_1.Q | _9_ | 0 | 0 | MC_Q
OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM
NODE | _9_.UIM | 791 | ? | 0 | 0 | EX3_COPY_0_COPY_0 | NULL | HPART_CREATED_1.Q | _9_ | 1 | 0 | MC_UIM
OUTPUT_NODE_TYPE | 4 | 0 | MC_EXPORT
NODE | _9_.EXP | 758 | ? | 0 | 0 | EX3_COPY_0_COPY_0 | NULL | _9_.EXP | _9_ | 4 | 0 | MC_EXPORT

SIGNAL_INSTANCE | HPART_CREATED_1.SI | _9_ | 0 | 2 | 3
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | sum<7>_BUFR.FBK | 784 | ? | 0 | 8 | EX3_COPY_0_COPY_0 | NULL | N45.Q | sum<7>_BUFR.MC |
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ex3.vm6 - 源码说明

本页面展示了「[VHDL经典设计26例]--在xilinx芯片上调试通过--[01--1位全加器][02--2选1多路选择器][03--8位硬件加法器][04--7段数码显示译码器][05--8位串入并出寄存器][」中的 ex3.vm6 源码文件，采用 VM6 编程语言编写，共 927 行代码。您可以在线阅读完整代码内容，也可以返回资源详情页下载完整源码包进行本地学习和开发。

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