ex3.mod

来自「[VHDL经典设计26例]--在xilinx芯片上调试通过--[01--1位全加」· MOD 代码 · 共 108 行

MODEL
MODEL_VERSION "v1998.8";
DESIGN "ex3";

/* port names and type */
INPUT S:PIN20 = a<0>;
INPUT S:PIN36 = b<0>;
INPUT S:PIN23 = a<1>;
INPUT S:PIN33 = b<1>;
INPUT S:PIN35 = b<2>;
INPUT S:PIN37 = b<3>;
INPUT S:PIN40 = b<4>;
INPUT S:PIN39 = b<5>;
INPUT S:PIN41 = b<6>;
INPUT S:PIN24 = a<2>;
INPUT S:PIN25 = a<3>;
INPUT S:PIN26 = a<4>;
INPUT S:PIN31 = a<5>;
INPUT S:PIN34 = a<6>;
INPUT S:PIN32 = a<7>;
INPUT S:PIN43 = b<7>;
OUTPUT S:PIN66 = sum<0>;
OUTPUT S:PIN69 = sum<1>;
OUTPUT S:PIN68 = sum<2>;
OUTPUT S:PIN71 = sum<3>;
OUTPUT S:PIN70 = sum<4>;
OUTPUT S:PIN72 = sum<5>;
OUTPUT S:PIN76 = sum<6>;
OUTPUT S:PIN77 = sum<7>;

/* timing arc definitions */
a<0>_sum<0>_delay: DELAY a<0> sum<0>;
b<0>_sum<0>_delay: DELAY b<0> sum<0>;
a<0>_sum<1>_delay: DELAY a<0> sum<1>;
b<0>_sum<1>_delay: DELAY b<0> sum<1>;
a<1>_sum<1>_delay: DELAY a<1> sum<1>;
b<1>_sum<1>_delay: DELAY b<1> sum<1>;
a<0>_sum<2>_delay: DELAY a<0> sum<2>;
b<0>_sum<2>_delay: DELAY b<0> sum<2>;
a<1>_sum<2>_delay: DELAY a<1> sum<2>;
b<1>_sum<2>_delay: DELAY b<1> sum<2>;
b<2>_sum<2>_delay: DELAY b<2> sum<2>;
a<2>_sum<2>_delay: DELAY a<2> sum<2>;
a<0>_sum<3>_delay: DELAY a<0> sum<3>;
b<0>_sum<3>_delay: DELAY b<0> sum<3>;
a<1>_sum<3>_delay: DELAY a<1> sum<3>;
b<1>_sum<3>_delay: DELAY b<1> sum<3>;
b<2>_sum<3>_delay: DELAY b<2> sum<3>;
b<3>_sum<3>_delay: DELAY b<3> sum<3>;
a<2>_sum<3>_delay: DELAY a<2> sum<3>;
a<3>_sum<3>_delay: DELAY a<3> sum<3>;
a<0>_sum<4>_delay: DELAY a<0> sum<4>;
b<0>_sum<4>_delay: DELAY b<0> sum<4>;
a<1>_sum<4>_delay: DELAY a<1> sum<4>;
b<1>_sum<4>_delay: DELAY b<1> sum<4>;
b<2>_sum<4>_delay: DELAY b<2> sum<4>;
b<3>_sum<4>_delay: DELAY b<3> sum<4>;
b<4>_sum<4>_delay: DELAY b<4> sum<4>;
a<2>_sum<4>_delay: DELAY a<2> sum<4>;
a<3>_sum<4>_delay: DELAY a<3> sum<4>;
a<4>_sum<4>_delay: DELAY a<4> sum<4>;
a<0>_sum<5>_delay: DELAY a<0> sum<5>;
b<0>_sum<5>_delay: DELAY b<0> sum<5>;
a<1>_sum<5>_delay: DELAY a<1> sum<5>;
b<1>_sum<5>_delay: DELAY b<1> sum<5>;
b<2>_sum<5>_delay: DELAY b<2> sum<5>;
b<3>_sum<5>_delay: DELAY b<3> sum<5>;
b<4>_sum<5>_delay: DELAY b<4> sum<5>;
b<5>_sum<5>_delay: DELAY b<5> sum<5>;
a<2>_sum<5>_delay: DELAY a<2> sum<5>;
a<3>_sum<5>_delay: DELAY a<3> sum<5>;
a<4>_sum<5>_delay: DELAY a<4> sum<5>;
a<5>_sum<5>_delay: DELAY a<5> sum<5>;
a<0>_sum<6>_delay: DELAY a<0> sum<6>;
b<0>_sum<6>_delay: DELAY b<0> sum<6>;
a<1>_sum<6>_delay: DELAY a<1> sum<6>;
b<1>_sum<6>_delay: DELAY b<1> sum<6>;
b<2>_sum<6>_delay: DELAY b<2> sum<6>;
b<3>_sum<6>_delay: DELAY b<3> sum<6>;
b<4>_sum<6>_delay: DELAY b<4> sum<6>;
b<5>_sum<6>_delay: DELAY b<5> sum<6>;
b<6>_sum<6>_delay: DELAY b<6> sum<6>;
a<2>_sum<6>_delay: DELAY a<2> sum<6>;
a<3>_sum<6>_delay: DELAY a<3> sum<6>;
a<4>_sum<6>_delay: DELAY a<4> sum<6>;
a<5>_sum<6>_delay: DELAY a<5> sum<6>;
a<6>_sum<6>_delay: DELAY a<6> sum<6>;
a<0>_sum<7>_delay: DELAY a<0> sum<7>;
b<0>_sum<7>_delay: DELAY b<0> sum<7>;
a<1>_sum<7>_delay: DELAY a<1> sum<7>;
b<1>_sum<7>_delay: DELAY b<1> sum<7>;
b<2>_sum<7>_delay: DELAY b<2> sum<7>;
b<3>_sum<7>_delay: DELAY b<3> sum<7>;
b<4>_sum<7>_delay: DELAY b<4> sum<7>;
b<5>_sum<7>_delay: DELAY b<5> sum<7>;
b<6>_sum<7>_delay: DELAY b<6> sum<7>;
a<2>_sum<7>_delay: DELAY a<2> sum<7>;
a<3>_sum<7>_delay: DELAY a<3> sum<7>;
a<4>_sum<7>_delay: DELAY a<4> sum<7>;
a<5>_sum<7>_delay: DELAY a<5> sum<7>;
a<6>_sum<7>_delay: DELAY a<6> sum<7>;
a<7>_sum<7>_delay: DELAY a<7> sum<7>;
b<7>_sum<7>_delay: DELAY b<7> sum<7>;

/* timing check arc definitions */

ENDMODEL