ex3.tim

来自「[VHDL经典设计26例]--在xilinx芯片上调试通过--[01--1位全加」· TIM 代码 · 共 82 行

                           Performance Summary Report
                           --------------------------

Design:     ex3
Device:     XC95108-7-PC84
Speed File: Version 3.0
Program:    Timing Report Generator:  version E.38
Date:       Tue Mar 11 22:37:30 2008

Performance Summary: 

Pad to Pad (tPD)                          :         23.5ns (3 macrocell levels)
Pad 'b<4>' to Pad 'sum<7>'                                        

--------------------------------------------------------------------------------
                            Pad to Pad (tPD) (nsec)

\ From      a     a     a     a     a     a     a     a     b     b     b     b
 \          <     <     <     <     <     <     <     <     <     <     <     <
  \         0     1     2     3     4     5     6     7     0     1     2     3
   \        >     >     >     >     >     >     >     >     >     >     >     >
    \                                                                          
     \                                                                         
      \                                                                        
  To   \------------------------------------------------------------------------

sum<0>    7.5                                             7.5                  
sum<1>    7.5   7.5                                       7.5   7.5            
sum<2>    9.5   9.5   9.5                                 9.5   9.5   9.5      
sum<3>    8.5   8.5   8.5  14.0                           8.5   8.5   8.5  14.0
sum<4>    8.5   8.5   8.5   9.5  18.0                     8.5   8.5   8.5   9.5
sum<5>    8.5   9.5   9.5   9.5  16.0  14.0               8.5   9.5   9.5   9.5
sum<6>   15.0  15.0  15.0  16.0  22.5  22.5  20.5        15.0  15.0  15.0  16.0
sum<7>   16.0  16.0  16.0  17.0  23.5  23.5  23.5  21.5  16.0  16.0  16.0  17.0

--------------------------------------------------------------------------------
                            Pad to Pad (tPD) (nsec)

\ From      b     b     b     b
 \          <     <     <     <
  \         4     5     6     7
   \        >     >     >     >
    \                          
     \                         
      \                        
  To   \------------------------

sum<0>                         
sum<1>                         
sum<2>                         
sum<3>                         
sum<4>   18.0                  
sum<5>   16.0  14.0            
sum<6>   22.5  22.5  20.5      
sum<7>   23.5  23.5  23.5  21.5

Path Type Definition: 

Pad to Pad (tPD) -                        Reports pad to pad paths that start 
                                          at input pads and end at output pads. 
                                          Paths are not traced through 
                                          registers. 

Clock Pad to Output Pad (tCO) -           Reports paths that start at input 
                                          pads trace through clock inputs of 
                                          registers and end at output pads. 
                                          Paths are not traced through PRE/CLR 
                                          inputs of registers. 

Setup to Clock at Pad (tSU) -             Reports external setup time of data 
                                          to clock at pad. Data path starts at 
                                          an input pad and end at register D/T 
                                          input. Clock path starts at input pad 
                                          and ends at the register clock input. 
                                          Paths are not traced through 
                                          registers. 

Clock to Setup (tCYC) -                   Register to register cycle time. 
                                          Include source register tCO and 
                                          destination register tSU.