ex3.rpt
来自「[VHDL经典设计26例]--在xilinx芯片上调试通过--[01--1位全加」· RPT 代码 · 共 681 行 · 第 1/3 页
RPT
681 行
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB3_1 (b)
(unused) 0 0 0 5 FB3_2 14 I/O
(unused) 0 0 0 5 FB3_3 15 I/O
(unused) 0 0 0 5 FB3_4 (b)
(unused) 0 0 0 5 FB3_5 17 I/O
(unused) 0 0 0 5 FB3_6 18 I/O
(unused) 0 0 0 5 FB3_7 (b)
(unused) 0 0 0 5 FB3_8 19 I/O
(unused) 0 0 0 5 FB3_9 20 I/O I
(unused) 0 0 0 5 FB3_10 (b)
(unused) 0 0 0 5 FB3_11 21 I/O
(unused) 0 0 0 5 FB3_12 23 I/O I
(unused) 0 0 0 5 FB3_13 (b)
(unused) 0 0 0 5 FB3_14 24 I/O I
(unused) 0 0 0 5 FB3_15 25 I/O I
(unused) 0 0 0 5 FB3_16 26 I/O I
(unused) 0 0 0 5 FB3_17 31 I/O I
(unused) 0 0 0 5 FB3_18 (b)
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK/FCLK - Global clock
O - Output GTS/FOE - Global 3state/output-enable
(b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB4 ***********************************
Number of function block inputs used/remaining: 9/27
Number of signals used by logic mapping into function block: 9
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 /\1 4 FB4_1 (b) (b)
(unused) 0 0 0 5 FB4_2 57 I/O
(unused) 0 0 0 5 FB4_3 58 I/O
(unused) 0 0 0 5 FB4_4 (b)
(unused) 0 0 0 5 FB4_5 61 I/O
(unused) 0 0 0 5 FB4_6 62 I/O
(unused) 0 0 0 5 FB4_7 (b)
(unused) 0 0 0 5 FB4_8 63 I/O
(unused) 0 0 0 5 FB4_9 65 I/O
(unused) 0 0 0 5 FB4_10 (b)
sum<0> 2 0 0 3 FB4_11 STD 66 I/O O
(unused) 0 0 \/4 1 FB4_12 67 I/O (b)
(unused) 0 0 \/5 0 FB4_13 (b) (b)
sum<2> 16 11<- 0 0 FB4_14 STD 68 I/O O
sum<1> 3 0 /\2 0 FB4_15 STD 69 I/O O
(unused) 0 0 \/5 0 FB4_16 (b) (b)
sum<4> 16 11<- 0 0 FB4_17 STD 70 I/O O
(unused) 0 0 /\5 0 FB4_18 (b) (b)
Signals Used by Logic in Function Block
1: "a<0>" 4: "a<3>" 7: "b<1>"
2: "a<1>" 5: "N_a<4>$X0$N_b<4>/N_a<4>$X0$N_b<4>_D"
8: "b<2>"
3: "a<2>" 6: "b<0>" 9: "b<3>"
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
sum<0> X....X.................................. 2 2
sum<2> XXX..XXX................................ 6 6
sum<1> XX...XX................................. 4 4
sum<4> XXXXXXXXX............................... 9 9
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK/FCLK - Global clock
O - Output GTS/FOE - Global 3state/output-enable
(b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB5 ***********************************
Number of function block inputs used/remaining: 0/36
Number of signals used by logic mapping into function block: 0
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB5_1 (b)
(unused) 0 0 0 5 FB5_2 32 I/O I
(unused) 0 0 0 5 FB5_3 33 I/O I
(unused) 0 0 0 5 FB5_4 (b)
(unused) 0 0 0 5 FB5_5 34 I/O I
(unused) 0 0 0 5 FB5_6 35 I/O I
(unused) 0 0 0 5 FB5_7 (b)
(unused) 0 0 0 5 FB5_8 36 I/O I
(unused) 0 0 0 5 FB5_9 37 I/O I
(unused) 0 0 0 5 FB5_10 (b)
(unused) 0 0 0 5 FB5_11 39 I/O I
(unused) 0 0 0 5 FB5_12 40 I/O I
(unused) 0 0 0 5 FB5_13 (b)
(unused) 0 0 0 5 FB5_14 41 I/O I
(unused) 0 0 0 5 FB5_15 43 I/O I
(unused) 0 0 0 5 FB5_16 (b)
(unused) 0 0 0 5 FB5_17 44 I/O
(unused) 0 0 0 5 FB5_18 (b)
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK/FCLK - Global clock
O - Output GTS/FOE - Global 3state/output-enable
(b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB6 ***********************************
Number of function block inputs used/remaining: 0/36
Number of signals used by logic mapping into function block: 0
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB6_1 (b)
(unused) 0 0 0 5 FB6_2 45 I/O
(unused) 0 0 0 5 FB6_3 46 I/O
(unused) 0 0 0 5 FB6_4 (b)
(unused) 0 0 0 5 FB6_5 47 I/O
(unused) 0 0 0 5 FB6_6 48 I/O
(unused) 0 0 0 5 FB6_7 (b)
(unused) 0 0 0 5 FB6_8 50 I/O
(unused) 0 0 0 5 FB6_9 51 I/O
(unused) 0 0 0 5 FB6_10 (b)
(unused) 0 0 0 5 FB6_11 52 I/O
(unused) 0 0 0 5 FB6_12 53 I/O
(unused) 0 0 0 5 FB6_13 (b)
(unused) 0 0 0 5 FB6_14 54 I/O
(unused) 0 0 0 5 FB6_15 55 I/O
(unused) 0 0 0 5 FB6_16 (b)
(unused) 0 0 0 5 FB6_17 56 I/O
(unused) 0 0 0 5 FB6_18 (b)
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK/FCLK - Global clock
O - Output GTS/FOE - Global 3state/output-enable
(b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
;;-----------------------------------------------------------------;;
; Implemented Equations.
"sum<0>" = "b<0>"
Xor "a<0>"
"sum<1>" = "a<0>" * "b<0>"
Xor "a<1>" * /"b<1>"
+ /"a<1>" * "b<1>"
"sum<2>" = /"a<0>" * /"a<1>" * /"b<2>" * "a<2>"
+ /"a<0>" * /"b<1>" * /"b<2>" * "a<2>"
+ /"b<0>" * /"a<1>" * /"b<2>" * "a<2>"
+ "a<1>" * "b<1>" * "b<2>" * "a<2>"
+ /"a<1>" * /"b<1>" * /"b<2>" * "a<2>"
;Imported pterms FB4_13
+ /"a<0>" * /"a<1>" * "b<2>" * /"a<2>"
+ /"a<0>" * /"b<1>" * "b<2>" * /"a<2>"
+ /"b<0>" * /"a<1>" * "b<2>" * /"a<2>"
+ /"b<0>" * /"b<1>" * /"b<2>" * "a<2>"
+ /"a<1>" * /"b<1>" * "b<2>" * /"a<2>"
;Imported pterms FB4_12
+ "a<0>" * "b<0>" * "a<1>" * "b<2>" * "a<2>"
+ "a<0>" * "b<0>" * "a<1>" * /"b<2>" * /"a<2>"
+ "a<0>" * "b<0>" * "b<1>" * "b<2>" * "a<2>"
+ "a<0>" * "b<0>" * "b<1>" * /"b<2>" * /"a<2>"
;Imported pterms FB4_15
+ /"b<0>" * /"b<1>" * "b<2>" * /"a<2>"
+ "a<1>" * "b<1>" * /"b<2>" * /"a<2>"
"sum<3>" = "N_a<3>$X0$N_b<3>/N_a<3>$X0$N_b<3>_D.FBK".LFBK
Xor "b<2>" * "a<2>"
+ "a<1>" * "b<1>" * "a<2>"
;Imported pterms FB2_1
+ "a<1>" * "b<1>" * "b<2>"
+ "a<0>" * "b<0>" * "a<1>" * "b<2>"
+ "a<0>" * "b<0>" * "a<1>" * "a<2>"
+ "a<0>" * "b<0>" * "b<1>" * "b<2>"
+ "a<0>" * "b<0>" * "b<1>" * "a<2>"
"sum<4>" = "N_a<4>$X0$N_b<4>/N_a<4>$X0$N_b<4>_D"
Xor "b<2>" * "a<2>" * "a<3>"
+ "a<1>" * "b<1>" * "b<2>" * "a<3>"
+ "a<1>" * "b<1>" * "a<2>" * "a<3>"
+ "a<0>" * "b<0>" * "a<1>" * "a<2>" * "a<3>"
;Imported pterms FB4_16
+ "b<2>" * "b<3>" * "a<2>"
+ "a<1>" * "b<1>" * "b<3>" * "a<2>"
+ "a<0>" * "b<0>" * "a<1>" * "b<2>" * "a<3>"
+ "a<0>" * "b<0>" * "b<1>" * "b<2>" * "a<3>"
+ "a<0>" * "b<0>" * "b<1>" * "a<2>" * "a<3>"
;Imported pterms FB4_18
+ "a<1>" * "b<1>" * "b<2>" * "b<3>"
+ "a<0>" * "b<0>" * "a<1>" * "b<2>" * "b<3>"
+ "a<0>" * "b<0>" * "a<1>" * "b<3>" * "a<2>"
+ "a<0>" * "b<0>" * "b<1>" * "b<2>" * "b<3>"
+ "a<0>" * "b<0>" * "b<1>" * "b<3>" * "a<2>"
;Imported pterms FB4_1
+ "b<3>" * "a<3>"
"sum<5>" = "N_a<5>$X0$N_b<5>/N_a<5>$X0$N_b<5>_D.FBK".LFBK
Xor "a<0>" * "b<0>" * "a<1>" * "b<2>" * "b<3>" *
"N_a<4>$X0$N_b<4>/N_a<4>$X0$N_b<4>_D.FBK".LFBK
+ "a<0>" * "b<0>" * "a<1>" * "b<3>" * "a<2>" *
"N_a<4>$X0$N_b<4>/N_a<4>$X0$N_b<4>_D.FBK".LFBK
+ "a<0>" * "b<0>" * "b<1>" * "b<2>" * "b<3>" *
"N_a<4>$X0$N_b<4>/N_a<4>$X0$N_b<4>_D.FBK".LFBK
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