ex3.rpt
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RPT
681 行
cpldfit: version E.38 Xilinx Inc.
Fitter Report
Design Name: ex3 Date: 3-11-2008, 10:37PM
Device Used: XC95108-7-PC84
Fitting Status: Successful
**************************** Resource Summary ****************************
Macrocells Product Terms Registers Pins Function Block
Used Used Used Used Inputs Used
15 /108 ( 13%) 111 /540 ( 20%) 0 /108 ( 0%) 24 /69 ( 34%) 32 /216 ( 14%)
PIN RESOURCES:
Signal Type Required Mapped | Pin Type Used Remaining
------------------------------------|---------------------------------------
Input : 16 16 | I/O : 22 41
Output : 8 8 | GCK/IO : 0 3
Bidirectional : 0 0 | GTS/IO : 2 0
GCK : 0 0 | GSR/IO : 0 1
GTS : 0 0 |
GSR : 0 0 |
---- ----
Total 24 24
MACROCELL RESOURCES:
Total Macrocells Available 108
Registered Macrocells 0
Non-registered Macrocell driving I/O 8
GLOBAL RESOURCES:
Global clock net(s) unused.
Global output enable net(s) unused.
Global set/reset net(s) unused.
POWER DATA:
There are 15 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
There are a total of 15 macrocells used (MC).
End of Resource Summary
**************************** Errors and Warnings *************************
WARNING:Cpld:939 - Unable to map all desired signals into function block, FB2,
because too many function block product terms are required. Buffering output
signal sum<7> to allow all signals assigned to this function block to be
placed.
WARNING:Cpld:939 - Unable to map all desired signals into function block, FB2,
because too many function block product terms are required. Buffering output
signal sum<6> to allow all signals assigned to this function block to be
placed.
***************Resources Used by Successfully Mapped Logic******************
** LOGIC **
Signal Total Signals Loc Pwr Slew Pin Pin Pin
Name Pt Used Mode Rate # Type Use
N_a<3>$X0$N_b<3>/N_a<3>$X0$N_b<3>_D 2 2 FB2_6 STD 75 I/O (b)
N_a<4>$X0$N_b<4>/N_a<4>$X0$N_b<4>_D 2 2 FB2_7 STD (b) (b)
N_a<5>$X0$N_b<5>/N_a<5>$X0$N_b<5>_D 2 2 FB2_12 STD 80 I/O (b)
N_a<6>$X0$N_b<6>/N_a<6>$X0$N_b<6>_D 2 2 FB2_13 STD (b) (b)
N_a<7>$X0$N_b<7>/N_a<7>$X0$N_b<7>_D 2 2 FB2_14 STD 81 I/O (b)
sum<0> 2 2 FB4_11 STD FAST 66 I/O O
sum<1> 3 4 FB4_15 STD FAST 69 I/O O
sum<2> 16 6 FB4_14 STD FAST 68 I/O O
sum<3> 8 7 FB2_2 STD FAST 71 I/O O
sum<4> 16 9 FB4_17 STD FAST 70 I/O O
sum<5> 17 11 FB2_3 STD FAST 72 I/O O
sum<6> 1 1 FB2_8 STD FAST 76 GTS/I/O O
sum<6>_BUFR.MC 18 13 FB2_10 STD (b) (b)
sum<7> 1 1 FB2_9 STD FAST 77 GTS/I/O O
sum<7>_BUFR.MC 19 15 FB2_16 STD 83 I/O (b)
** INPUTS **
Signal Loc Pin Pin Pin
Name # Type Use
a<0> FB3_9 20 I/O I
a<1> FB3_12 23 I/O I
a<2> FB3_14 24 I/O I
a<3> FB3_15 25 I/O I
a<4> FB3_16 26 I/O I
a<5> FB3_17 31 I/O I
a<6> FB5_5 34 I/O I
a<7> FB5_2 32 I/O I
b<0> FB5_8 36 I/O I
b<1> FB5_3 33 I/O I
b<2> FB5_6 35 I/O I
b<3> FB5_9 37 I/O I
b<4> FB5_12 40 I/O I
b<5> FB5_11 39 I/O I
b<6> FB5_14 41 I/O I
b<7> FB5_15 43 I/O I
End of Resources Used by Successfully Mapped Logic
*********************Function Block Resource Summary***********************
Function # of FB Inputs Signals Total O/IO IO
Block Macrocells Used Used Pt Used Req Avail
FB1 0 0 0 0 0/0 12
FB2 11 23 23 74 4/0 12
FB3 0 0 0 0 0/0 12
FB4 4 9 9 37 4/0 11
FB5 0 0 0 0 0/0 11
FB6 0 0 0 0 0/0 11
---- ----- ----- -----
15 111 8/0 69
*********************************** FB1 ***********************************
Number of function block inputs used/remaining: 0/36
Number of signals used by logic mapping into function block: 0
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB1_1 (b)
(unused) 0 0 0 5 FB1_2 1 I/O
(unused) 0 0 0 5 FB1_3 2 I/O
(unused) 0 0 0 5 FB1_4 (b)
(unused) 0 0 0 5 FB1_5 3 I/O
(unused) 0 0 0 5 FB1_6 4 I/O
(unused) 0 0 0 5 FB1_7 (b)
(unused) 0 0 0 5 FB1_8 5 I/O
(unused) 0 0 0 5 FB1_9 6 I/O
(unused) 0 0 0 5 FB1_10 (b)
(unused) 0 0 0 5 FB1_11 7 I/O
(unused) 0 0 0 5 FB1_12 9 GCK/I/O
(unused) 0 0 0 5 FB1_13 (b)
(unused) 0 0 0 5 FB1_14 10 GCK/I/O
(unused) 0 0 0 5 FB1_15 11 I/O
(unused) 0 0 0 5 FB1_16 12 GCK/I/O
(unused) 0 0 0 5 FB1_17 13 I/O
(unused) 0 0 0 5 FB1_18 (b)
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK/FCLK - Global clock
O - Output GTS/FOE - Global 3state/output-enable
(b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB2 ***********************************
Number of function block inputs used/remaining: 23/13
Number of signals used by logic mapping into function block: 23
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 \/5 0 FB2_1 (b) (b)
sum<3> 8 5<- \/2 0 FB2_2 STD 71 I/O O
sum<5> 17 12<- 0 0 FB2_3 STD 72 I/O O
(unused) 0 0 /\5 0 FB2_4 (b) (b)
(unused) 0 0 /\5 0 FB2_5 74 GSR/I/O (b)
N_a<3>$X0$N_b<3>/N_a<3>$X0$N_b<3>_D
2 0 0 3 FB2_6 STD 75 I/O (b)
N_a<4>$X0$N_b<4>/N_a<4>$X0$N_b<4>_D
2 0 0 3 FB2_7 STD (b) (b)
sum<6> 1 0 \/1 3 FB2_8 STD 76 GTS/I/O O
sum<7> 1 1<- \/5 0 FB2_9 STD 77 GTS/I/O O
sum<6>_BUFR.MC 18 13<- 0 0 FB2_10 STD (b) (b)
(unused) 0 0 /\5 0 FB2_11 79 I/O (b)
N_a<5>$X0$N_b<5>/N_a<5>$X0$N_b<5>_D
2 0 /\3 0 FB2_12 STD 80 I/O (b)
N_a<6>$X0$N_b<6>/N_a<6>$X0$N_b<6>_D
2 0 0 3 FB2_13 STD (b) (b)
N_a<7>$X0$N_b<7>/N_a<7>$X0$N_b<7>_D
2 0 \/3 0 FB2_14 STD 81 I/O (b)
(unused) 0 0 \/5 0 FB2_15 82 I/O (b)
sum<7>_BUFR.MC 19 14<- 0 0 FB2_16 STD 83 I/O (b)
(unused) 0 0 /\5 0 FB2_17 84 I/O (b)
(unused) 0 0 /\1 4 FB2_18 (b) (b)
Signals Used by Logic in Function Block
1: "a<0>" 9: "N_a<5>$X0$N_b<5>/N_a<5>$X0$N_b<5>_D.FBK".LFBK
17: "b<3>"
2: "a<1>" 10: "a<6>" 18: "b<4>"
3: "a<2>" 11: "N_a<6>$X0$N_b<6>/N_a<6>$X0$N_b<6>_D.FBK".LFBK
19: "b<5>"
4: "a<3>" 12: "a<7>" 20: "b<6>"
5: "N_a<3>$X0$N_b<3>/N_a<3>$X0$N_b<3>_D.FBK".LFBK
13: "N_a<7>$X0$N_b<7>/N_a<7>$X0$N_b<7>_D.FBK".LFBK
21: "b<7>"
6: "a<4>" 14: "b<0>" 22: "sum<6>_BUFR.FBK".LFBK
7: "N_a<4>$X0$N_b<4>/N_a<4>$X0$N_b<4>_D.FBK".LFBK
15: "b<1>" 23: "sum<7>_BUFR.FBK".LFBK
8: "a<5>" 16: "b<2>"
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
sum<3> XXX.X........XXX........................ 7 7
sum<5> XXXX.XX.X....XXXX....................... 11 11
N_a<3>$X0$N_b<3>/N_a<3>$X0$N_b<3>_D
...X............X....................... 2 2
N_a<4>$X0$N_b<4>/N_a<4>$X0$N_b<4>_D
.....X...........X...................... 2 2
sum<6> .....................X.................. 1 1
sum<7> ......................X................. 1 1
sum<6>_BUFR.MC XXXX.XXXX.X..XXXX....................... 13 13
N_a<5>$X0$N_b<5>/N_a<5>$X0$N_b<5>_D
.......X..........X..................... 2 2
N_a<6>$X0$N_b<6>/N_a<6>$X0$N_b<6>_D
.........X.........X.................... 2 2
N_a<7>$X0$N_b<7>/N_a<7>$X0$N_b<7>_D
...........X........X................... 2 2
sum<7>_BUFR.MC XXXX.XXXXXX.XXXXX....................... 15 15
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK/FCLK - Global clock
O - Output GTS/FOE - Global 3state/output-enable
(b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB3 ***********************************
Number of function block inputs used/remaining: 0/36
Number of signals used by logic mapping into function block: 0
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