ex11.gyd

来自「[VHDL经典设计26例]--在xilinx芯片上调试通过--[01--1位全加」· GYD 代码 · 共 42 行

Pin Freeze File:  version E.38

957284 XC9572-7-PC84
clk S:PIN10
row<7> S:PIN77
row<3> S:PIN71
row<6> S:PIN76
row<4> S:PIN70
row<5> S:PIN72
col<0> S:PIN45
col<1> S:PIN46
col<2> S:PIN47
col<3> S:PIN48
col<4> S:PIN51
col<5> S:PIN53
col<6> S:PIN55
row<2> S:PIN68
row<1> S:PIN69
row<0> S:PIN66
col<7> S:PIN57


;The remaining section of the .gyd file is for documentation purposes only.
;It shows where your internal equations were placed in the last successful fit.


PARTITION FB2_2 "N_row<2>$BUF0"
PARTITION FB2_4 "N_row<2>" "C1/N23$BUF0" "C1/N16$BUF0" "C1/N23"
		 "C1/N30"
PARTITION FB2_11 "C1/N16"
PARTITION FB2_16 "cnt<2>" "cnt<1>" "cnt<0>"
PARTITION FB3_16 N29

PARTITION FB4_1 N30
PARTITION FB4_3 N36
PARTITION FB4_5 N32
PARTITION FB4_7 N40 N34
PARTITION FB4_10 net0 N38
PARTITION FB4_17 "N_row<2>$BUF1"