ex11.mod

来自「[VHDL经典设计26例]--在xilinx芯片上调试通过--[01--1位全加」· MOD 代码 · 共 42 行

MODEL
MODEL_VERSION "v1998.8";
DESIGN "ex11";

/* port names and type */
INPUT S:PIN10 = clk;
OUTPUT S:PIN77 = row<7>;
OUTPUT S:PIN48 = col<3>;
OUTPUT S:PIN51 = col<4>;
OUTPUT S:PIN53 = col<5>;
OUTPUT S:PIN55 = col<6>;
OUTPUT S:PIN46 = col<1>;
OUTPUT S:PIN47 = col<2>;
OUTPUT S:PIN76 = row<6>;
OUTPUT S:PIN72 = row<5>;
OUTPUT S:PIN45 = col<0>;
OUTPUT S:PIN71 = row<3>;
OUTPUT S:PIN70 = row<4>;
OUTPUT S:PIN57 = col<7>;
OUTPUT S:PIN68 = row<2>;
OUTPUT S:PIN69 = row<1>;
OUTPUT S:PIN66 = row<0>;

/* timing arc definitions */
clk_row<7>_delay: DELAY clk row<7>;
clk_col<3>_delay: DELAY clk col<3>;
clk_col<4>_delay: DELAY clk col<4>;
clk_col<5>_delay: DELAY clk col<5>;
clk_col<6>_delay: DELAY clk col<6>;
clk_col<1>_delay: DELAY clk col<1>;
clk_col<2>_delay: DELAY clk col<2>;
clk_row<6>_delay: DELAY clk row<6>;
clk_row<5>_delay: DELAY clk row<5>;
clk_col<0>_delay: DELAY clk col<0>;
clk_row<3>_delay: DELAY clk row<3>;
clk_row<4>_delay: DELAY clk row<4>;
clk_col<7>_delay: DELAY clk col<7>;

/* timing check arc definitions */

ENDMODEL