ex11.rpt
来自「[VHDL经典设计26例]--在xilinx芯片上调试通过--[01--1位全加」· RPT 代码 · 共 416 行 · 第 1/2 页
RPT
416 行
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK/FCLK - Global clock
O - Output GTS/FOE - Global 3state/output-enable
(b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB4 ***********************************
Number of function block inputs used/remaining: 3/33
Number of signals used by logic mapping into function block: 3
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
col<1> 1 0 0 4 FB4_1 STD 46 I/O O
(unused) 0 0 0 5 FB4_2 44 I/O
col<4> 1 0 0 4 FB4_3 STD 51 I/O O
(unused) 0 0 0 5 FB4_4 52 I/O
col<2> 1 0 0 4 FB4_5 STD 47 I/O O
(unused) 0 0 0 5 FB4_6 54 I/O
col<6> 1 0 0 4 FB4_7 STD 55 I/O O
col<3> 1 0 0 4 FB4_8 STD 48 I/O O
(unused) 0 0 0 5 FB4_9 50 I/O
col<7> 1 0 0 4 FB4_10 STD 57 I/O O
col<5> 1 0 0 4 FB4_11 STD 53 I/O O
(unused) 0 0 0 5 FB4_12 58 I/O
(unused) 0 0 0 5 FB4_13 61 I/O
(unused) 0 0 0 5 FB4_14 56 I/O
(unused) 0 0 0 5 FB4_15 65 I/O
(unused) 0 0 0 5 FB4_16 62 I/O
row<0> 0 0 0 5 FB4_17 STD 66 I/O O
(unused) 0 0 0 5 FB4_18 (b)
Signals Used by Logic in Function Block
1: "cnt<0>" 2: "cnt<1>" 3: "cnt<2>"
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
col<1> XXX..................................... 3 3
col<4> XXX..................................... 3 3
col<2> XXX..................................... 3 3
col<6> XXX..................................... 3 3
col<3> XXX..................................... 3 3
col<7> XXX..................................... 3 3
col<5> XXX..................................... 3 3
row<0> ........................................ 0 0
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK/FCLK - Global clock
O - Output GTS/FOE - Global 3state/output-enable
(b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
;;-----------------------------------------------------------------;;
; Implemented Equations.
/"row<7>" = /"cnt<1>.FBK".LFBK * /"cnt<2>.FBK".LFBK
+ "cnt<1>.FBK".LFBK * "cnt<2>.FBK".LFBK *
"cnt<0>.FBK".LFBK
/"row<3>" = /"cnt<1>.FBK".LFBK * /"cnt<2>.FBK".LFBK
+ "cnt<1>.FBK".LFBK * "cnt<2>.FBK".LFBK *
"cnt<0>.FBK".LFBK
"row<6>" = /"cnt<1>.FBK".LFBK * "cnt<2>.FBK".LFBK *
/"cnt<0>.FBK".LFBK
+ /"cnt<1>.FBK".LFBK * /"cnt<2>.FBK".LFBK *
"cnt<0>.FBK".LFBK
"row<4>" = /"cnt<1>.FBK".LFBK * "cnt<2>.FBK".LFBK *
/"cnt<0>.FBK".LFBK
+ /"cnt<1>.FBK".LFBK * /"cnt<2>.FBK".LFBK *
"cnt<0>.FBK".LFBK
"row<5>" = /"cnt<1>.FBK".LFBK * /"cnt<0>.FBK".LFBK
"col<0>" = "cnt<0>" * "cnt<1>" * "cnt<2>"
"col<1>" = /"cnt<0>" * "cnt<1>" * "cnt<2>"
"col<2>" = "cnt<0>" * /"cnt<1>" * "cnt<2>"
"col<3>" = /"cnt<0>" * /"cnt<1>" * "cnt<2>"
"col<4>" = "cnt<0>" * "cnt<1>" * /"cnt<2>"
"col<5>" = /"cnt<0>" * "cnt<1>" * /"cnt<2>"
"col<6>" = "cnt<0>" * /"cnt<1>" * /"cnt<2>"
"row<2>" = Gnd
"row<1>" = Gnd
"row<0>" = Gnd
"cnt<0>" := /"cnt<0>.FBK".LFBK
"cnt<0>".CLKF = clk ;FCLK/GCK
"cnt<0>".PRLD = GND
"cnt<1>".T = "cnt<0>.FBK".LFBK
"cnt<1>".CLKF = clk ;FCLK/GCK
"cnt<1>".PRLD = GND
"cnt<2>".T = "cnt<1>.FBK".LFBK * "cnt<0>.FBK".LFBK
"cnt<2>".CLKF = clk ;FCLK/GCK
"cnt<2>".PRLD = GND
"col<7>" = /"cnt<0>" * /"cnt<1>" * /"cnt<2>"
**************************** Device Pin Out ****************************
Device : XC9572-7-PC84
r r
o o
w w
T c T G T T T T T T T T T T T T T V < < T
I l I N I I I I I I I I I I I I I C 7 6 I
E k E D E E E E E E E E E E E E E C > > E
--------------------------------------------------------------
/11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 \
TIE | 12 74 | TIE
TIE | 13 73 | VCC
TIE | 14 72 | row<5>
TIE | 15 71 | row<3>
GND | 16 70 | row<4>
TIE | 17 69 | row<1>
TIE | 18 68 | row<2>
TIE | 19 67 | TIE
TIE | 20 66 | row<0>
TIE | 21 XC9572-7-PC84 65 | TIE
VCC | 22 64 | VCC
TIE | 23 63 | TIE
TIE | 24 62 | TIE
TIE | 25 61 | TIE
TIE | 26 60 | GND
GND | 27 59 | TDO
TDI | 28 58 | TIE
TMS | 29 57 | col<7>
TCK | 30 56 | TIE
TIE | 31 55 | col<6>
TIE | 32 54 | TIE
\ 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 /
--------------------------------------------------------------
T T T T T V T T T G T T c c c c G T c T c
I I I I I C I I I N I I o o o o N I o I o
E E E E E C E E E D E E l l l l D E l E l
< < < < < <
0 1 2 3 4 5
> > > > > >
Legend : NC = Not Connected, unbonded pin
TIE = Tie pin to GND or board trace driven to valid logic level
VCC = Dedicated Power Pin
GND = Dedicated Ground Pin
TDI = Test Data In, JTAG pin
TDO = Test Data Out, JTAG pin
TCK = Test Clock, JTAG pin
TMS = Test Mode Select, JTAG pin
PE = Port Enable pin
PROHIBITED = User reserved pin
**************************** Compiler Options ****************************
Following is a list of all global compiler options used by the fitter run.
Device(s) Specified : XC9572-7-PC84
Use Timing Constraints : ON
Use Design Location Constraints : ON
Create Programmable Ground Pins : OFF
Use Advanced Fitting : ON
Use Local Feedback : ON
Use Pin Feedback : ON
Default Power Setting : STD
Default Output Slew Rate : FAST
Guide File Used : NONE
Multi Level Logic Optimization : ON
Timing Optimization : ON
Power/Slew Optimization : OFF
High Fitting Effort : ON
Automatic Wire-ANDing : ON
Xor Synthesis : ON
D/T Synthesis : ON
Use Boolean Minimization : ON
Global Clock(GCK) Optimization : ON
Global Set/Reset(GSR) Optimization : ON
Global Output Enable(GTS) Optimization : ON
Collapsing pterm limit : 25
Collapsing input limit : 36
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