ex11.rpt
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RPT
416 行
cpldfit: version E.38 Xilinx Inc.
Fitter Report
Design Name: ex11 Date: 3-18-2008, 8:50AM
Device Used: XC9572-7-PC84
Fitting Status: Successful
**************************** Resource Summary ****************************
Macrocells Product Terms Registers Pins Function Block
Used Used Used Used Inputs Used
19 /72 ( 26%) 20 /360 ( 5%) 3 /72 ( 4%) 17 /69 ( 24%) 9 /144 ( 6%)
PIN RESOURCES:
Signal Type Required Mapped | Pin Type Used Remaining
------------------------------------|---------------------------------------
Input : 0 0 | I/O : 14 49
Output : 16 16 | GCK/IO : 1 2
Bidirectional : 0 0 | GTS/IO : 2 0
GCK : 1 1 | GSR/IO : 0 1
GTS : 0 0 |
GSR : 0 0 |
---- ----
Total 17 17
MACROCELL RESOURCES:
Total Macrocells Available 72
Registered Macrocells 3
Non-registered Macrocell driving I/O 16
GLOBAL RESOURCES:
Signal 'clk' mapped onto global clock net GCK2.
Global output enable net(s) unused.
Global set/reset net(s) unused.
POWER DATA:
There are 19 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
There are a total of 19 macrocells used (MC).
End of Resource Summary
***************Resources Used by Successfully Mapped Logic******************
** LOGIC **
Signal Total Signals Loc Pwr Slew Pin Pin Pin
Name Pt Used Mode Rate # Type Use
cnt<0> 1 1 FB2_18 STD (b) (b)
cnt<1> 1 1 FB2_17 STD 84 I/O (b)
cnt<2> 1 2 FB2_16 STD 82 I/O (b)
col<0> 1 3 FB3_16 STD FAST 45 I/O O
col<1> 1 3 FB4_1 STD FAST 46 I/O O
col<2> 1 3 FB4_5 STD FAST 47 I/O O
col<3> 1 3 FB4_8 STD FAST 48 I/O O
col<4> 1 3 FB4_3 STD FAST 51 I/O O
col<5> 1 3 FB4_11 STD FAST 53 I/O O
col<6> 1 3 FB4_7 STD FAST 55 I/O O
col<7> 1 3 FB4_10 STD FAST 57 I/O O
row<0> 0 0 FB4_17 STD FAST 66 I/O O
row<1> 0 0 FB2_2 STD FAST 69 I/O O
row<2> 0 0 FB2_4 STD FAST 68 I/O O
row<3> 2 3 FB2_6 STD FAST 71 I/O O
row<4> 2 3 FB2_5 STD FAST 70 I/O O
row<5> 1 2 FB2_8 STD FAST 72 I/O O
row<6> 2 3 FB2_7 STD FAST 76 GTS/I/O O
row<7> 2 3 FB2_11 STD FAST 77 GTS/I/O O
** INPUTS **
Signal Loc Pin Pin Pin
Name # Type Use
clk FB1_11 10 GCK/I/O GCK
End of Resources Used by Successfully Mapped Logic
*********************Function Block Resource Summary***********************
Function # of FB Inputs Signals Total O/IO IO
Block Macrocells Used Used Pt Used Req Avail
FB1 0 0 0 0 0/0 18
FB2 10 3 3 12 7/0 17
FB3 1 3 3 1 1/0 17
FB4 8 3 3 7 8/0 17
---- ----- ----- -----
19 20 16/0 69
*********************************** FB1 ***********************************
Number of function block inputs used/remaining: 0/36
Number of signals used by logic mapping into function block: 0
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB1_1 4 I/O
(unused) 0 0 0 5 FB1_2 1 I/O
(unused) 0 0 0 5 FB1_3 6 I/O
(unused) 0 0 0 5 FB1_4 7 I/O
(unused) 0 0 0 5 FB1_5 2 I/O
(unused) 0 0 0 5 FB1_6 3 I/O
(unused) 0 0 0 5 FB1_7 11 I/O
(unused) 0 0 0 5 FB1_8 5 I/O
(unused) 0 0 0 5 FB1_9 9 GCK/I/O
(unused) 0 0 0 5 FB1_10 13 I/O
(unused) 0 0 0 5 FB1_11 10 GCK/I/O GCK
(unused) 0 0 0 5 FB1_12 18 I/O
(unused) 0 0 0 5 FB1_13 20 I/O
(unused) 0 0 0 5 FB1_14 12 GCK/I/O
(unused) 0 0 0 5 FB1_15 14 I/O
(unused) 0 0 0 5 FB1_16 23 I/O
(unused) 0 0 0 5 FB1_17 15 I/O
(unused) 0 0 0 5 FB1_18 24 I/O
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK/FCLK - Global clock
O - Output GTS/FOE - Global 3state/output-enable
(b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB2 ***********************************
Number of function block inputs used/remaining: 3/33
Number of signals used by logic mapping into function block: 3
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB2_1 63 I/O
row<1> 0 0 0 5 FB2_2 STD 69 I/O O
(unused) 0 0 0 5 FB2_3 67 I/O
row<2> 0 0 0 5 FB2_4 STD 68 I/O O
row<4> 2 0 0 3 FB2_5 STD 70 I/O O
row<3> 2 0 0 3 FB2_6 STD 71 I/O O
row<6> 2 0 0 3 FB2_7 STD 76 GTS/I/O O
row<5> 1 0 0 4 FB2_8 STD 72 I/O O
(unused) 0 0 0 5 FB2_9 74 GSR/I/O
(unused) 0 0 0 5 FB2_10 75 I/O
row<7> 2 0 0 3 FB2_11 STD 77 GTS/I/O O
(unused) 0 0 0 5 FB2_12 79 I/O
(unused) 0 0 0 5 FB2_13 80 I/O
(unused) 0 0 0 5 FB2_14 81 I/O
(unused) 0 0 0 5 FB2_15 83 I/O
cnt<2> 1 0 0 4 FB2_16 STD 82 I/O (b)
cnt<1> 1 0 0 4 FB2_17 STD 84 I/O (b)
cnt<0> 1 0 0 4 FB2_18 STD (b) (b)
Signals Used by Logic in Function Block
1: "cnt<0>.FBK".LFBK 2: "cnt<1>.FBK".LFBK 3: "cnt<2>.FBK".LFBK
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
row<1> ........................................ 0 0
row<2> ........................................ 0 0
row<4> XXX..................................... 3 3
row<3> XXX..................................... 3 3
row<6> XXX..................................... 3 3
row<5> XX...................................... 2 2
row<7> XXX..................................... 3 3
cnt<2> XX...................................... 2 2
cnt<1> X....................................... 1 1
cnt<0> X....................................... 1 1
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK/FCLK - Global clock
O - Output GTS/FOE - Global 3state/output-enable
(b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB3 ***********************************
Number of function block inputs used/remaining: 3/33
Number of signals used by logic mapping into function block: 3
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB3_1 25 I/O
(unused) 0 0 0 5 FB3_2 17 I/O
(unused) 0 0 0 5 FB3_3 31 I/O
(unused) 0 0 0 5 FB3_4 32 I/O
(unused) 0 0 0 5 FB3_5 19 I/O
(unused) 0 0 0 5 FB3_6 34 I/O
(unused) 0 0 0 5 FB3_7 35 I/O
(unused) 0 0 0 5 FB3_8 21 I/O
(unused) 0 0 0 5 FB3_9 26 I/O
(unused) 0 0 0 5 FB3_10 40 I/O
(unused) 0 0 0 5 FB3_11 33 I/O
(unused) 0 0 0 5 FB3_12 41 I/O
(unused) 0 0 0 5 FB3_13 43 I/O
(unused) 0 0 0 5 FB3_14 36 I/O
(unused) 0 0 0 5 FB3_15 37 I/O
col<0> 1 0 0 4 FB3_16 STD 45 I/O O
(unused) 0 0 0 5 FB3_17 39 I/O
(unused) 0 0 0 5 FB3_18 (b)
Signals Used by Logic in Function Block
1: "cnt<0>" 2: "cnt<1>" 3: "cnt<2>"
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
col<0> XXX..................................... 3 3
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