time_sim.edn
来自「[VHDL经典设计26例]--在xilinx芯片上调试通过--[01--1位全加」· EDN 代码 · 共 1,650 行 · 第 1/5 页
EDN
1,650 行
(net (rename row_0__ "row<0>") (joined (portRef row_0__) (portRef PAD (instanceRef row_0__PAD)) (portRef OUT (instanceRef row_0___103)) ) ) (net C1_N16_Q (joined (portRef IN (instanceRef row_7___8)) (portRef OUT (instanceRef C1_N16_Q_9)) ) ) (net C1_N16_Q_0 (joined (portRef IN (instanceRef C1_N16_Q_9)) (portRef OUT (instanceRef C1_N16_REG)) ) ) (net C1_N16_D (joined (portRef IN (instanceRef C1_N16_REG)) (portRef OUT (instanceRef C1_N16_XOR)) ) ) (net C1_N16_D1 (joined (portRef OUT (instanceRef C1_N16_D1_10)) (portRef IN (instanceRef NlwInverterBlock_C1_N16_XOR_IN0)) ) ) (net cnt_2__FBK (joined (portRef IN0 (instanceRef C1_N16_D2_PT_1_12)) (portRef OUT (instanceRef cnt_2__FBK_19)) (portRef IN0 (instanceRef C1_N23_D2_PT_0_65)) (portRef IN0 (instanceRef C1_N16_BUF0_D2_PT_1_82)) (portRef IN0 (instanceRef C1_N23_BUF0_D2_PT_0_87)) (portRef IN (instanceRef NlwInverterBlock_C1_N16_D2_PT_0_IN0)) (portRef IN (instanceRef NlwInverterBlock_C1_N23_D2_PT_1_IN0)) (portRef IN (instanceRef NlwInverterBlock_C1_N16_BUF0_D2_PT_0_IN0)) (portRef IN (instanceRef NlwInverterBlock_C1_N23_BUF0_D2_PT_1_IN0)) ) ) (net cnt_1__FBK (joined (portRef IN2 (instanceRef C1_N16_D2_PT_1_12)) (portRef IN1 (instanceRef cnt_2__D2_PT_0_16)) (portRef OUT (instanceRef cnt_1__FBK_31)) (portRef IN2 (instanceRef C1_N16_BUF0_D2_PT_1_82)) (portRef IN (instanceRef NlwInverterBlock_C1_N16_D2_PT_0_IN1)) (portRef IN (instanceRef NlwInverterBlock_C1_N23_D2_PT_0_IN2)) (portRef IN (instanceRef NlwInverterBlock_C1_N23_D2_PT_1_IN2)) (portRef IN (instanceRef NlwInverterBlock_C1_N30_D2_PT_0_IN1)) (portRef IN (instanceRef NlwInverterBlock_C1_N16_BUF0_D2_PT_0_IN1)) (portRef IN (instanceRef NlwInverterBlock_C1_N23_BUF0_D2_PT_0_IN2)) (portRef IN (instanceRef NlwInverterBlock_C1_N23_BUF0_D2_PT_1_IN2)) ) ) (net C1_N16_D2_PT_0 (joined (portRef OUT (instanceRef C1_N16_D2_PT_0_11)) (portRef IN0 (instanceRef C1_N16_D2_13)) ) ) (net cnt_0__FBK (joined (portRef IN1 (instanceRef C1_N16_D2_PT_1_12)) (portRef IN0 (instanceRef cnt_2__D2_PT_0_16)) (portRef OUT (instanceRef cnt_0__FBK_24)) (portRef IN0 (instanceRef cnt_1__D2_PT_0_28)) (portRef IN1 (instanceRef cnt_1__D2_PT_0_28)) (portRef IN1 (instanceRef C1_N23_D2_PT_1_66)) (portRef IN1 (instanceRef C1_N16_BUF0_D2_PT_1_82)) (portRef IN1 (instanceRef C1_N23_BUF0_D2_PT_1_88)) (portRef IN (instanceRef NlwInverterBlock_cnt_0__D2_PT_0_IN0)) (portRef IN (instanceRef NlwInverterBlock_cnt_0__D2_PT_0_IN1)) (portRef IN (instanceRef NlwInverterBlock_C1_N23_D2_PT_0_IN1)) (portRef IN (instanceRef NlwInverterBlock_C1_N30_D2_PT_0_IN0)) (portRef IN (instanceRef NlwInverterBlock_C1_N23_BUF0_D2_PT_0_IN1)) ) ) (net C1_N16_D2_PT_1 (joined (portRef OUT (instanceRef C1_N16_D2_PT_1_12)) (portRef IN1 (instanceRef C1_N16_D2_13)) ) ) (net C1_N16_D2 (joined (portRef OUT (instanceRef C1_N16_D2_13)) (portRef IN1 (instanceRef C1_N16_XOR)) ) ) (net cnt_2__Q (joined (portRef IN (instanceRef cnt_2___14)) (portRef OUT (instanceRef cnt_2__REG)) (portRef IN1 (instanceRef cnt_2__D_18)) (portRef IN (instanceRef cnt_2__FBK_19)) ) ) (net (rename cnt_2__ "cnt<2>") (joined (portRef OUT (instanceRef cnt_2___14)) (portRef IN2 (instanceRef N34_D2_PT_0_35)) (portRef IN2 (instanceRef N30_D2_PT_0_55)) (portRef IN2 (instanceRef N32_D2_PT_0_60)) (portRef IN2 (instanceRef N29_D2_PT_0_76)) (portRef IN (instanceRef NlwInverterBlock_N36_D2_PT_0_IN2)) (portRef IN (instanceRef NlwInverterBlock_N38_D2_PT_0_IN2)) (portRef IN (instanceRef NlwInverterBlock_N40_D2_PT_0_IN2)) (portRef IN (instanceRef NlwInverterBlock_net0_D2_PT_0_IN2)) ) ) (net cnt_2__D (joined (portRef IN (instanceRef cnt_2__REG)) (portRef OUT (instanceRef cnt_2__D_18)) ) ) (net FCLKIO_0 (joined (portRef CLK (instanceRef cnt_2__REG)) (portRef CLK (instanceRef cnt_0__REG)) (portRef OUT (instanceRef FCLKIO_0_25)) (portRef CLK (instanceRef cnt_1__REG)) ) ) (net cnt_2__D1 (joined (portRef OUT (instanceRef cnt_2__D1_15)) (portRef IN0 (instanceRef cnt_2__XOR)) ) ) (net cnt_2__D2_PT_0 (joined (portRef OUT (instanceRef cnt_2__D2_PT_0_16)) (portRef IN0 (instanceRef cnt_2__D2_17)) (portRef IN1 (instanceRef cnt_2__D2_17)) ) ) (net cnt_2__D2 (joined (portRef OUT (instanceRef cnt_2__D2_17)) (portRef IN1 (instanceRef cnt_2__XOR)) ) ) (net cnt_2__D_TFF (joined (portRef IN0 (instanceRef cnt_2__D_18)) (portRef OUT (instanceRef cnt_2__XOR)) ) ) (net cnt_0__Q (joined (portRef IN (instanceRef cnt_0___20)) (portRef OUT (instanceRef cnt_0__REG)) (portRef IN (instanceRef cnt_0__FBK_24)) ) ) (net (rename cnt_0__ "cnt<0>") (joined (portRef OUT (instanceRef cnt_0___20)) (portRef IN0 (instanceRef N36_D2_PT_0_40)) (portRef IN0 (instanceRef N40_D2_PT_0_50)) (portRef IN0 (instanceRef N32_D2_PT_0_60)) (portRef IN0 (instanceRef N29_D2_PT_0_76)) (portRef IN (instanceRef NlwInverterBlock_N34_D2_PT_0_IN0)) (portRef IN (instanceRef NlwInverterBlock_N38_D2_PT_0_IN0)) (portRef IN (instanceRef NlwInverterBlock_N30_D2_PT_0_IN0)) (portRef IN (instanceRef NlwInverterBlock_net0_D2_PT_0_IN0)) ) ) (net cnt_0__D (joined (portRef IN (instanceRef cnt_0__REG)) (portRef OUT (instanceRef cnt_0__XOR)) ) ) (net cnt_0__D1 (joined (portRef OUT (instanceRef cnt_0__D1_21)) (portRef IN0 (instanceRef cnt_0__XOR)) ) ) (net cnt_0__D2_PT_0 (joined (portRef OUT (instanceRef cnt_0__D2_PT_0_22)) (portRef IN0 (instanceRef cnt_0__D2_23)) (portRef IN1 (instanceRef cnt_0__D2_23)) ) ) (net cnt_0__D2 (joined (portRef OUT (instanceRef cnt_0__D2_23)) (portRef IN1 (instanceRef cnt_0__XOR)) ) ) (net cnt_1__Q (joined (portRef IN (instanceRef cnt_1___26)) (portRef OUT (instanceRef cnt_1__REG)) (portRef IN1 (instanceRef cnt_1__D_30)) (portRef IN (instanceRef cnt_1__FBK_31)) ) ) (net (rename cnt_1__ "cnt<1>") (joined (portRef OUT (instanceRef cnt_1___26)) (portRef IN1 (instanceRef N36_D2_PT_0_40)) (portRef IN1 (instanceRef N38_D2_PT_0_45)) (portRef IN1 (instanceRef N30_D2_PT_0_55)) (portRef IN1 (instanceRef N29_D2_PT_0_76)) (portRef IN (instanceRef NlwInverterBlock_N34_D2_PT_0_IN1)) (portRef IN (instanceRef NlwInverterBlock_N40_D2_PT_0_IN1)) (portRef IN (instanceRef NlwInverterBlock_N32_D2_PT_0_IN1)) (portRef IN (instanceRef NlwInverterBlock_net0_D2_PT_0_IN1)) ) ) (net cnt_1__D (joined (portRef IN (instanceRef cnt_1__REG)) (portRef OUT (instanceRef cnt_1__D_30)) ) ) (net cnt_1__D1 (joined (portRef OUT (instanceRef cnt_1__D1_27)) (portRef IN0 (instanceRef cnt_1__XOR)) ) ) (net cnt_1__D2_PT_0 (joined (portRef OUT (instanceRef cnt_1__D2_PT_0_28)) (portRef IN0 (instanceRef cnt_1__D2_29)) (portRef IN1 (instanceRef cnt_1__D2_29)) ) ) (net cnt_1__D2 (joined (portRef OUT (instanceRef cnt_1__D2_29)) (portRef IN1 (instanceRef cnt_1__XOR)) ) ) (net cnt_1__D_TFF (joined (portRef IN0 (instanceRef cnt_1__D_30)) (portRef OUT (instanceRef cnt_1__XOR)) ) ) (net N34_Q (joined (portRef IN (instanceRef col_3___32)) (portRef OUT (instanceRef N34_Q_33)) ) ) (net N34_Q_1 (joined (portRef IN (instanceRef N34_Q_33)) (portRef OUT (instanceRef N34_REG)) ) ) (net N34_D (joined (portRef IN (instanceRef N34_REG)) (portRef OUT (instanceRef N34_XOR)) ) ) (net N34_D1 (joined (portRef OUT (instanceRef N34_D1_34)) (portRef IN0 (instanceRef N34_XOR)) ) ) (net N34_D2_PT_0 (joined (portRef OUT (instanceRef N34_D2_PT_0_35)) (portRef IN0 (instanceRef N34_D2_36)) (portRef IN1 (instanceRef N34_D2_36)) ) ) (net N34_D2 (joined (portRef OUT (instanceRef N34_D2_36)) (portRef IN1 (instanceRef N34_XOR)) ) ) (net N36_Q (joined (portRef IN (instanceRef col_4___37)) (portRef OUT (instanceRef N36_Q_38)) ) ) (net N36_Q_2 (joined (portRef IN (instanceRef N36_Q_38)) (portRef OUT (instanceRef N36_REG)) ) ) (net N36_D (joined (portRef IN (instanceRef N36_REG)) (portRef OUT (instanceRef N36_XOR)) ) ) (net N36_D1 (joined (portRef OUT (instanceRef N36_D1_39)) (portRef IN0 (instanceRef N36_XOR)) ) ) (net N36_D2_PT_0 (joined (portRef OUT (instanceRef N36_D2_PT_0_40)) (portRef IN0 (instanceRef N36_D2_41)) (portRef IN1 (instanceRef N36_D2_41)) ) ) (net N36_D2 (joined (portRef OUT (instanceRef N36_D2_41)) (portRef IN1 (instanceRef N36_XOR)) ) ) (net N38_Q (joined (portRef IN (instanceRef col_5___42)) (portRef OUT (instanceRef N38_Q_43))
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