time_sim.edn
来自「[VHDL经典设计26例]--在xilinx芯片上调试通过--[01--1位全加」· EDN 代码 · 共 1,650 行 · 第 1/5 页
EDN
1,650 行
(instance (rename col_7___90 "col_7_&_90") (viewRef view_1 (cellRef x_buf (libraryRef SIMPRIMS))) (portInstance OUT (property RISE (integer 2500) (unit TIME) (owner "Xilinx")) (property FALL (integer 2500) (unit TIME) (owner "Xilinx")) ) ) (instance net0_Q_91 (viewRef view_1 (cellRef x_buf (libraryRef SIMPRIMS))) ) (instance net0_REG (viewRef view_1 (cellRef x_buf (libraryRef SIMPRIMS))) (portInstance OUT (property RISE (integer 500) (unit TIME) (owner "Xilinx")) (property FALL (integer 500) (unit TIME) (owner "Xilinx")) ) ) (instance net0_D1_92 (viewRef view_1 (cellRef x_or2 (libraryRef SIMPRIMS))) ) (instance net0_D2_PT_0_93 (viewRef view_1 (cellRef x_and3 (libraryRef SIMPRIMS))) (portInstance IN0 (property RISE (integer 10000) (unit TIME) (owner "Xilinx")) (property FALL (integer 10000) (unit TIME) (owner "Xilinx")) ) (portInstance IN1 (property RISE (integer 10000) (unit TIME) (owner "Xilinx")) (property FALL (integer 10000) (unit TIME) (owner "Xilinx")) ) (portInstance IN2 (property RISE (integer 10000) (unit TIME) (owner "Xilinx")) (property FALL (integer 10000) (unit TIME) (owner "Xilinx")) ) ) (instance net0_D2_94 (viewRef view_1 (cellRef x_or2 (libraryRef SIMPRIMS))) ) (instance net0_XOR (viewRef view_1 (cellRef x_xor2 (libraryRef SIMPRIMS))) ) (instance row_2__PAD (viewRef view_1 (cellRef x_opad (libraryRef SIMPRIMS))) ) (instance (rename row_2___95 "row_2_&_95") (viewRef view_1 (cellRef x_buf (libraryRef SIMPRIMS))) (portInstance OUT (property RISE (integer 2500) (unit TIME) (owner "Xilinx")) (property FALL (integer 2500) (unit TIME) (owner "Xilinx")) ) ) (instance N_row_2__Q_96 (viewRef view_1 (cellRef x_buf (libraryRef SIMPRIMS))) ) (instance N_row_2__REG (viewRef view_1 (cellRef x_buf (libraryRef SIMPRIMS))) (portInstance OUT (property RISE (integer 500) (unit TIME) (owner "Xilinx")) (property FALL (integer 500) (unit TIME) (owner "Xilinx")) ) ) (instance N_row_2__D1_97 (viewRef view_1 (cellRef x_or2 (libraryRef SIMPRIMS))) ) (instance N_row_2__D2_98 (viewRef view_1 (cellRef x_or2 (libraryRef SIMPRIMS))) ) (instance N_row_2__XOR (viewRef view_1 (cellRef x_xor2 (libraryRef SIMPRIMS))) ) (instance row_1__PAD (viewRef view_1 (cellRef x_opad (libraryRef SIMPRIMS))) ) (instance (rename row_1___99 "row_1_&_99") (viewRef view_1 (cellRef x_buf (libraryRef SIMPRIMS))) (portInstance OUT (property RISE (integer 2500) (unit TIME) (owner "Xilinx")) (property FALL (integer 2500) (unit TIME) (owner "Xilinx")) ) ) (instance N_row_2__BUF0_100 (viewRef view_1 (cellRef x_buf (libraryRef SIMPRIMS))) ) (instance N_row_2__BUF0_REG (viewRef view_1 (cellRef x_buf (libraryRef SIMPRIMS))) (portInstance OUT (property RISE (integer 500) (unit TIME) (owner "Xilinx")) (property FALL (integer 500) (unit TIME) (owner "Xilinx")) ) ) (instance N_row_2__BUF0_D1_101 (viewRef view_1 (cellRef x_or2 (libraryRef SIMPRIMS))) ) (instance N_row_2__BUF0_D2_102 (viewRef view_1 (cellRef x_or2 (libraryRef SIMPRIMS))) ) (instance N_row_2__BUF0_XOR (viewRef view_1 (cellRef x_xor2 (libraryRef SIMPRIMS))) ) (instance row_0__PAD (viewRef view_1 (cellRef x_opad (libraryRef SIMPRIMS))) ) (instance (rename row_0___103 "row_0_&_103") (viewRef view_1 (cellRef x_buf (libraryRef SIMPRIMS))) (portInstance OUT (property RISE (integer 2500) (unit TIME) (owner "Xilinx")) (property FALL (integer 2500) (unit TIME) (owner "Xilinx")) ) ) (instance N_row_2__BUF1_104 (viewRef view_1 (cellRef x_buf (libraryRef SIMPRIMS))) ) (instance N_row_2__BUF1_REG (viewRef view_1 (cellRef x_buf (libraryRef SIMPRIMS))) (portInstance OUT (property RISE (integer 500) (unit TIME) (owner "Xilinx")) (property FALL (integer 500) (unit TIME) (owner "Xilinx")) ) ) (instance N_row_2__BUF1_D1_105 (viewRef view_1 (cellRef x_or2 (libraryRef SIMPRIMS))) ) (instance N_row_2__BUF1_D2_106 (viewRef view_1 (cellRef x_or2 (libraryRef SIMPRIMS))) ) (instance N_row_2__BUF1_XOR (viewRef view_1 (cellRef x_xor2 (libraryRef SIMPRIMS))) ) (instance NlwInverterBlock_C1_N16_D2_PT_0_IN0 (viewRef view_1 (cellRef x_inv (libraryRef SIMPRIMS))) ) (instance NlwInverterBlock_C1_N16_D2_PT_0_IN1 (viewRef view_1 (cellRef x_inv (libraryRef SIMPRIMS))) ) (instance NlwInverterBlock_C1_N16_XOR_IN0 (viewRef view_1 (cellRef x_inv (libraryRef SIMPRIMS))) ) (instance NlwInverterBlock_cnt_0__D2_PT_0_IN0 (viewRef view_1 (cellRef x_inv (libraryRef SIMPRIMS))) ) (instance NlwInverterBlock_cnt_0__D2_PT_0_IN1 (viewRef view_1 (cellRef x_inv (libraryRef SIMPRIMS))) ) (instance NlwInverterBlock_N34_D2_PT_0_IN0 (viewRef view_1 (cellRef x_inv (libraryRef SIMPRIMS))) ) (instance NlwInverterBlock_N34_D2_PT_0_IN1 (viewRef view_1 (cellRef x_inv (libraryRef SIMPRIMS))) ) (instance NlwInverterBlock_N36_D2_PT_0_IN2 (viewRef view_1 (cellRef x_inv (libraryRef SIMPRIMS))) ) (instance NlwInverterBlock_N38_D2_PT_0_IN0 (viewRef view_1 (cellRef x_inv (libraryRef SIMPRIMS))) ) (instance NlwInverterBlock_N38_D2_PT_0_IN2 (viewRef view_1 (cellRef x_inv (libraryRef SIMPRIMS))) ) (instance NlwInverterBlock_N40_D2_PT_0_IN1 (viewRef view_1 (cellRef x_inv (libraryRef SIMPRIMS))) ) (instance NlwInverterBlock_N40_D2_PT_0_IN2 (viewRef view_1 (cellRef x_inv (libraryRef SIMPRIMS))) ) (instance NlwInverterBlock_N30_D2_PT_0_IN0 (viewRef view_1 (cellRef x_inv (libraryRef SIMPRIMS))) ) (instance NlwInverterBlock_N32_D2_PT_0_IN1 (viewRef view_1 (cellRef x_inv (libraryRef SIMPRIMS))) ) (instance NlwInverterBlock_C1_N23_D2_PT_0_IN1 (viewRef view_1 (cellRef x_inv (libraryRef SIMPRIMS))) ) (instance NlwInverterBlock_C1_N23_D2_PT_0_IN2 (viewRef view_1 (cellRef x_inv (libraryRef SIMPRIMS))) ) (instance NlwInverterBlock_C1_N23_D2_PT_1_IN0 (viewRef view_1 (cellRef x_inv (libraryRef SIMPRIMS))) ) (instance NlwInverterBlock_C1_N23_D2_PT_1_IN2 (viewRef view_1 (cellRef x_inv (libraryRef SIMPRIMS))) ) (instance NlwInverterBlock_C1_N30_D2_PT_0_IN0 (viewRef view_1 (cellRef x_inv (libraryRef SIMPRIMS))) ) (instance NlwInverterBlock_C1_N30_D2_PT_0_IN1 (viewRef view_1 (cellRef x_inv (libraryRef SIMPRIMS))) ) (instance NlwInverterBlock_C1_N16_BUF0_D2_PT_0_IN0 (viewRef view_1 (cellRef x_inv (libraryRef SIMPRIMS))) ) (instance NlwInverterBlock_C1_N16_BUF0_D2_PT_0_IN1 (viewRef view_1 (cellRef x_inv (libraryRef SIMPRIMS))) ) (instance NlwInverterBlock_C1_N16_BUF0_XOR_IN0 (viewRef view_1 (cellRef x_inv (libraryRef SIMPRIMS))) ) (instance NlwInverterBlock_C1_N23_BUF0_D2_PT_0_IN1 (viewRef view_1 (cellRef x_inv (libraryRef SIMPRIMS))) ) (instance NlwInverterBlock_C1_N23_BUF0_D2_PT_0_IN2 (viewRef view_1 (cellRef x_inv (libraryRef SIMPRIMS))) ) (instance NlwInverterBlock_C1_N23_BUF0_D2_PT_1_IN0 (viewRef view_1 (cellRef x_inv (libraryRef SIMPRIMS))) ) (instance NlwInverterBlock_C1_N23_BUF0_D2_PT_1_IN2 (viewRef view_1 (cellRef x_inv (libraryRef SIMPRIMS))) ) (instance NlwInverterBlock_net0_D2_PT_0_IN0 (viewRef view_1 (cellRef x_inv (libraryRef SIMPRIMS))) ) (instance NlwInverterBlock_net0_D2_PT_0_IN1 (viewRef view_1 (cellRef x_inv (libraryRef SIMPRIMS))) ) (instance NlwInverterBlock_net0_D2_PT_0_IN2 (viewRef view_1 (cellRef x_inv (libraryRef SIMPRIMS))) ) (net (rename row_7__ "row<7>") (joined (portRef row_7__) (portRef PAD (instanceRef row_7__PAD)) (portRef OUT (instanceRef row_7___8)) ) ) (net (rename col_3__ "col<3>") (joined (portRef col_3__) (portRef PAD (instanceRef col_3__PAD)) (portRef OUT (instanceRef col_3___32)) ) ) (net (rename col_4__ "col<4>") (joined (portRef col_4__) (portRef PAD (instanceRef col_4__PAD)) (portRef OUT (instanceRef col_4___37)) ) ) (net (rename col_5__ "col<5>") (joined (portRef col_5__) (portRef PAD (instanceRef col_5__PAD)) (portRef OUT (instanceRef col_5___42)) ) ) (net (rename col_6__ "col<6>") (joined (portRef col_6__) (portRef PAD (instanceRef col_6__PAD)) (portRef OUT (instanceRef col_6___47)) ) ) (net (rename col_1__ "col<1>") (joined (portRef col_1__) (portRef PAD (instanceRef col_1__PAD)) (portRef OUT (instanceRef col_1___52)) ) ) (net (rename col_2__ "col<2>") (joined (portRef col_2__) (portRef PAD (instanceRef col_2__PAD)) (portRef OUT (instanceRef col_2___57)) ) ) (net (rename row_6__ "row<6>") (joined (portRef row_6__) (portRef PAD (instanceRef row_6__PAD)) (portRef OUT (instanceRef row_6___62)) ) ) (net clk (joined (portRef clk) (portRef PAD (instanceRef clk_PAD)) (portRef IN (instanceRef FCLKIO_0_25)) ) ) (net (rename row_5__ "row<5>") (joined (portRef row_5__) (portRef PAD (instanceRef row_5__PAD)) (portRef OUT (instanceRef row_5___68)) ) ) (net (rename col_0__ "col<0>") (joined (portRef col_0__) (portRef PAD (instanceRef col_0__PAD)) (portRef OUT (instanceRef col_0___73)) ) ) (net (rename row_3__ "row<3>") (joined (portRef row_3__) (portRef PAD (instanceRef row_3__PAD)) (portRef OUT (instanceRef row_3___78)) ) ) (net (rename row_4__ "row<4>") (joined (portRef row_4__) (portRef PAD (instanceRef row_4__PAD)) (portRef OUT (instanceRef row_4___84)) ) ) (net (rename col_7__ "col<7>") (joined (portRef col_7__) (portRef PAD (instanceRef col_7__PAD)) (portRef OUT (instanceRef col_7___90)) ) ) (net (rename row_2__ "row<2>") (joined (portRef row_2__) (portRef PAD (instanceRef row_2__PAD)) (portRef OUT (instanceRef row_2___95)) ) ) (net (rename row_1__ "row<1>") (joined (portRef row_1__) (portRef PAD (instanceRef row_1__PAD)) (portRef OUT (instanceRef row_1___99)) ) )
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