testctl.out

来自「[VHDL经典设计26例]--在xilinx芯片上调试通过--[01--1位全加」· OUT 代码 · 共 17 行

Inferred memory devices in process 
	in routine testctl line 16 in file
         'D:/temp/eda6000/xc95/ex10/testctl.vhd'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|     div2clk_reg     | Flip-flop |   1   |  -  | -  | N  | N  | N  | N  | Y  |
===============================================================================

div2clk_reg
-----------
    Sync-toggle: true


Writing to hnl file 'd:\temp\EDA6000\XC95\EX10\ex10/workdirs/WORK/testctl.hnl'