ex10.data

[VHDL经典设计26例]--在xilinx芯片上调试通过--[01--1位全加器][02--2选1多路选择器][03--8位硬件加法器][04--7段数码显示译码器][05--8位串入并出寄存器][

MODELDATA
MODELDATA_VERSION "v1998.8"
DESIGN "ex10";

/* port drive, load, max capacitance and max transition in data file */
PORTDATA
uclk: MAXTRANS(0.0);
clk1Hz: MAXTRANS(0.0);
p_cnt_en: MAXTRANS(0.0);
p_rst_cnt: MAXTRANS(0.0);
led0<0>: MAXTRANS(0.0);
led0<1>: MAXTRANS(0.0);
led0<2>: MAXTRANS(0.0);
led0<3>: MAXTRANS(0.0);
led1<0>: MAXTRANS(0.0);
led1<1>: MAXTRANS(0.0);
led1<2>: MAXTRANS(0.0);
led1<3>: MAXTRANS(0.0);
led2<0>: MAXTRANS(0.0);
led2<1>: MAXTRANS(0.0);
led2<2>: MAXTRANS(0.0);
led2<3>: MAXTRANS(0.0);
led3<0>: MAXTRANS(0.0);
led3<1>: MAXTRANS(0.0);
led3<2>: MAXTRANS(0.0);
led3<3>: MAXTRANS(0.0);
p_load: MAXTRANS(0.0);
ENDPORTDATA

/* timing arc data */
TIMINGDATA

ARCDATA
clk1Hz_p_rst_cnt_delay:
CELL_RISE(scalar) {
  VALUES("7.5");
}
CELL_FALL(scalar) {
  VALUES("7.5");
}
ENDARCDATA

ARCDATA
clk1Hz_p_cnt_en_delay:
CELL_RISE(scalar) {
  VALUES("4.5");
}
CELL_FALL(scalar) {
  VALUES("4.5");
}
ENDARCDATA

ARCDATA
clk1Hz_p_rst_cnt_delay:
CELL_RISE(scalar) {
  VALUES("11");
}
CELL_FALL(scalar) {
  VALUES("11");
}
ENDARCDATA

ARCDATA
clk1Hz_led0<0>_delay:
CELL_RISE(scalar) {
  VALUES("12");
}
CELL_FALL(scalar) {
  VALUES("12");
}
ENDARCDATA

ARCDATA
clk1Hz_led0<1>_delay:
CELL_RISE(scalar) {
  VALUES("13");
}
CELL_FALL(scalar) {
  VALUES("13");
}
ENDARCDATA

ARCDATA
clk1Hz_led0<2>_delay:
CELL_RISE(scalar) {
  VALUES("13");
}
CELL_FALL(scalar) {
  VALUES("13");
}
ENDARCDATA

ARCDATA
clk1Hz_led0<3>_delay:
CELL_RISE(scalar) {
  VALUES("13");
}
CELL_FALL(scalar) {
  VALUES("13");
}
ENDARCDATA

ARCDATA
clk1Hz_led1<0>_delay:
CELL_RISE(scalar) {
  VALUES("13");
}
CELL_FALL(scalar) {
  VALUES("13");
}
ENDARCDATA

ARCDATA
clk1Hz_led1<1>_delay:
CELL_RISE(scalar) {
  VALUES("13");
}
CELL_FALL(scalar) {
  VALUES("13");
}
ENDARCDATA

ARCDATA
clk1Hz_led1<2>_delay:
CELL_RISE(scalar) {
  VALUES("13");
}
CELL_FALL(scalar) {
  VALUES("13");
}
ENDARCDATA

ARCDATA
clk1Hz_led1<3>_delay:
CELL_RISE(scalar) {
  VALUES("13");
}
CELL_FALL(scalar) {
  VALUES("13");
}
ENDARCDATA

ARCDATA
clk1Hz_led2<0>_delay:
CELL_RISE(scalar) {
  VALUES("13");
}
CELL_FALL(scalar) {
  VALUES("13");
}
ENDARCDATA

ARCDATA
clk1Hz_led2<1>_delay:
CELL_RISE(scalar) {
  VALUES("13");
}
CELL_FALL(scalar) {
  VALUES("13");
}
ENDARCDATA

ARCDATA
clk1Hz_led2<2>_delay:
CELL_RISE(scalar) {
  VALUES("13");
}
CELL_FALL(scalar) {
  VALUES("13");
}
ENDARCDATA

ARCDATA
clk1Hz_led2<3>_delay:
CELL_RISE(scalar) {
  VALUES("13");
}
CELL_FALL(scalar) {
  VALUES("13");
}
ENDARCDATA

ARCDATA
clk1Hz_led3<0>_delay:
CELL_RISE(scalar) {
  VALUES("13");
}
CELL_FALL(scalar) {
  VALUES("13");
}
ENDARCDATA

ARCDATA
clk1Hz_led3<1>_delay:
CELL_RISE(scalar) {
  VALUES("13");
}
CELL_FALL(scalar) {
  VALUES("13");
}
ENDARCDATA

ARCDATA
clk1Hz_led3<2>_delay:
CELL_RISE(scalar) {
  VALUES("13");
}
CELL_FALL(scalar) {
  VALUES("13");
}
ENDARCDATA

ARCDATA
clk1Hz_led3<3>_delay:
CELL_RISE(scalar) {
  VALUES("13");
}
CELL_FALL(scalar) {
  VALUES("13");
}
ENDARCDATA

ARCDATA
clk1Hz_p_load_delay:
CELL_RISE(scalar) {
  VALUES("4.5");
}
CELL_FALL(scalar) {
  VALUES("4.5");
}
ENDARCDATA

ENDTIMINGDATA
ENDMODELDATA