ex10.rpt

来自「[VHDL经典设计26例]--在xilinx芯片上调试通过--[01--1位全加」· RPT 代码 · 共 629 行 · 第 1/3 页

RPT
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123
    cout0.PRLD  =  GND    

 cout1  :=  cout1.FBK.LFBK * /p_cnt_en.PIN
	+ "dout1<0>" * /"dout1<2>" * "dout1<3>" * 
	/"dout1<1>.FBK".LFBK * p_cnt_en.PIN
    cout1.CLKF  =  cout0
    cout1.RSTF  =  /clk1Hz * /p_cnt_en.PIN
    cout1.PRLD  =  GND    

 cout2  :=  cout2.FBK.LFBK * /p_cnt_en.PIN
	+ "dout2<0>" * /"dout2<2>" * /"dout2<1>" * 
	"dout2<3>" * p_cnt_en.PIN
    cout2.CLKF  =  cout1.FBK.LFBK
    cout2.RSTF  =  /clk1Hz * /p_cnt_en.PIN
    cout2.PRLD  =  GND    

 "dout0<0>".T  =  N_p_cnt_en.FBK.LFBK
    "dout0<0>".CLKF  =  uclk	;FCLK/GCK
    "dout0<0>".RSTF  =  /clk1Hz * /N_p_cnt_en.FBK.LFBK
    "dout0<0>".PRLD  =  GND    

 "dout0<1>".T  =  "dout0<0>" * "dout0<2>.FBK".LFBK * p_cnt_en.PIN
	+ "dout0<0>" * "dout0<1>.FBK".LFBK * p_cnt_en.PIN
	+ "dout0<0>" * /"dout0<3>.FBK".LFBK * p_cnt_en.PIN
    "dout0<1>".CLKF  =  uclk	;FCLK/GCK
    "dout0<1>".RSTF  =  /clk1Hz * /p_cnt_en.PIN
    "dout0<1>".PRLD  =  GND    

 "dout0<2>".T  =  "dout0<0>" * "dout0<1>.FBK".LFBK * p_cnt_en.PIN
    "dout0<2>".CLKF  =  uclk	;FCLK/GCK
    "dout0<2>".RSTF  =  /clk1Hz * /p_cnt_en.PIN
    "dout0<2>".PRLD  =  GND    

 "dout0<3>".T  =  "dout0<0>" * "dout0<2>.FBK".LFBK * 
	"dout0<1>.FBK".LFBK * p_cnt_en.PIN
	+ "dout0<0>" * /"dout0<2>.FBK".LFBK * 
	/"dout0<1>.FBK".LFBK * "dout0<3>.FBK".LFBK * p_cnt_en.PIN
    "dout0<3>".CLKF  =  uclk	;FCLK/GCK
    "dout0<3>".RSTF  =  /clk1Hz * /p_cnt_en.PIN
    "dout0<3>".PRLD  =  GND    

 "dout1<0>".T  =  N_p_cnt_en.FBK.LFBK
    "dout1<0>".CLKF  =  cout0
    "dout1<0>".RSTF  =  /clk1Hz * /N_p_cnt_en.FBK.LFBK
    "dout1<0>".PRLD  =  GND    

 "dout1<1>".T  =  "dout1<0>" * "dout1<2>" * p_cnt_en.PIN
	+ "dout1<0>" * /"dout1<3>" * p_cnt_en.PIN
	+ "dout1<0>" * "dout1<1>.FBK".LFBK * p_cnt_en.PIN
    "dout1<1>".CLKF  =  cout0
    "dout1<1>".RSTF  =  /clk1Hz * /p_cnt_en.PIN
    "dout1<1>".PRLD  =  GND    

 "dout1<2>".T  =  "dout1<0>" * "dout1<1>" * p_cnt_en.PIN
    "dout1<2>".CLKF  =  cout0.FBK.LFBK
    "dout1<2>".RSTF  =  /clk1Hz * /p_cnt_en.PIN
    "dout1<2>".PRLD  =  GND    

 "dout1<3>".T  =  "dout1<0>" * "dout1<1>" * "dout1<2>.FBK".LFBK * 
	p_cnt_en.PIN
	+ "dout1<0>" * /"dout1<1>" * /"dout1<2>.FBK".LFBK * 
	"dout1<3>.FBK".LFBK * p_cnt_en.PIN
    "dout1<3>".CLKF  =  cout0.FBK.LFBK
    "dout1<3>".RSTF  =  /clk1Hz * /p_cnt_en.PIN
    "dout1<3>".PRLD  =  GND    

 "dout2<0>".T  =  p_cnt_en.PIN
    "dout2<0>".CLKF  =  cout1
    "dout2<0>".RSTF  =  /clk1Hz * /p_cnt_en.PIN
    "dout2<0>".PRLD  =  GND    

 "dout2<1>".T  =  "dout2<0>.FBK".LFBK * "dout2<1>.FBK".LFBK * 
	p_cnt_en.PIN
	+ "dout2<0>.FBK".LFBK * "dout2<2>.FBK".LFBK * 
	p_cnt_en.PIN
	+ "dout2<0>.FBK".LFBK * /"dout2<3>.FBK".LFBK * 
	p_cnt_en.PIN
    "dout2<1>".CLKF  =  cout1
    "dout2<1>".RSTF  =  /clk1Hz * /p_cnt_en.PIN
    "dout2<1>".PRLD  =  GND    

 "dout2<2>".T  =  "dout2<0>.FBK".LFBK * "dout2<1>.FBK".LFBK * 
	p_cnt_en.PIN
    "dout2<2>".CLKF  =  cout1
    "dout2<2>".RSTF  =  /clk1Hz * /p_cnt_en.PIN
    "dout2<2>".PRLD  =  GND    

 "dout2<3>".T  =  "dout2<0>.FBK".LFBK * "dout2<1>.FBK".LFBK * 
	"dout2<2>.FBK".LFBK * p_cnt_en.PIN
	+ "dout2<0>.FBK".LFBK * /"dout2<1>.FBK".LFBK * 
	/"dout2<2>.FBK".LFBK * "dout2<3>.FBK".LFBK * p_cnt_en.PIN
    "dout2<3>".CLKF  =  cout1
    "dout2<3>".RSTF  =  /clk1Hz * /p_cnt_en.PIN
    "dout2<3>".PRLD  =  GND    

 "dout3<0>".T  =  p_cnt_en.PIN
    "dout3<0>".CLKF  =  cout2
    "dout3<0>".RSTF  =  /clk1Hz * /p_cnt_en.PIN
    "dout3<0>".PRLD  =  GND    

 "dout3<1>".T  =  "dout3<0>.FBK".LFBK * "dout3<1>.FBK".LFBK * 
	p_cnt_en.PIN
	+ "dout3<0>.FBK".LFBK * "dout3<2>.FBK".LFBK * 
	p_cnt_en.PIN
	+ "dout3<0>.FBK".LFBK * /"dout3<3>.FBK".LFBK * 
	p_cnt_en.PIN
    "dout3<1>".CLKF  =  cout2
    "dout3<1>".RSTF  =  /clk1Hz * /p_cnt_en.PIN
    "dout3<1>".PRLD  =  GND    

 "dout3<2>".T  =  "dout3<0>.FBK".LFBK * "dout3<1>.FBK".LFBK * 
	p_cnt_en.PIN
    "dout3<2>".CLKF  =  cout2
    "dout3<2>".RSTF  =  /clk1Hz * /p_cnt_en.PIN
    "dout3<2>".PRLD  =  GND    

 "dout3<3>".T  =  "dout3<0>.FBK".LFBK * "dout3<1>.FBK".LFBK * 
	"dout3<2>.FBK".LFBK * p_cnt_en.PIN
	+ "dout3<0>.FBK".LFBK * /"dout3<1>.FBK".LFBK * 
	/"dout3<2>.FBK".LFBK * "dout3<3>.FBK".LFBK * p_cnt_en.PIN
    "dout3<3>".CLKF  =  cout2
    "dout3<3>".RSTF  =  /clk1Hz * /p_cnt_en.PIN
    "dout3<3>".PRLD  =  GND    

****************************  Device Pin Out ****************************

Device : XC9572-7-PC84


                           l     l     l  l  l  l  l  l     l  l     
         c                 e     e     e  e  e  e  e  e     e  e     
         l                 d     d     d  d  d  d  d  d     d  d     
         k  u              3     3     3  3  2  2  2  2     1  1     
      T  1  c  G  T  T  T  <  T  <  T  <  <  <  <  <  <  V  <  <  T  
      I  H  l  N  I  I  I  3  I  2  I  0  1  2  3  0  1  C  3  2  I  
      E  z  k  D  E  E  E  >  E  >  E  >  >  >  >  >  >  C  >  >  E  
      --------------------------------------------------------------  
     /11 10 9  8  7  6  5  4  3  2  1  84 83 82 81 80 79 78 77 76 75 \
TIE | 12                                                          74 | TIE
TIE | 13                                                          73 | VCC
TIE | 14                                                          72 | led1<1>
TIE | 15                                                          71 | led0<3>
GND | 16                                                          70 | led1<0>
TIE | 17                                                          69 | led0<1>
TIE | 18                                                          68 | led0<2>
TIE | 19                                                          67 | TIE
TIE | 20                                                          66 | led0<0>
TIE | 21                        XC9572-7-PC84                     65 | TIE
VCC | 22                                                          64 | VCC
TIE | 23                                                          63 | TIE
TIE | 24                                                          62 | TIE
TIE | 25                                                          61 | TIE
TIE | 26                                                          60 | GND
GND | 27                                                          59 | TDO
TDI | 28                                                          58 | p_load
TMS | 29                                                          57 | TIE
TCK | 30                                                          56 | p_rst_cnt
TIE | 31                                                          55 | TIE
TIE | 32                                                          54 | TIE
    \ 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 /
      --------------------------------------------------------------  
      T  T  T  T  T  V  T  T  T  G  T  T  T  T  T  T  G  T  T  p  T  
      I  I  I  I  I  C  I  I  I  N  I  I  I  I  I  I  N  I  I  _  I  
      E  E  E  E  E  C  E  E  E  D  E  E  E  E  E  E  D  E  E  c  E  
                                                               n     
                                                               t     
                                                               _     
                                                               e     
                                                               n     


Legend :  NC  = Not Connected, unbonded pin
         TIE  = Tie pin to GND or board trace driven to valid logic level
         VCC  = Dedicated Power Pin
         GND  = Dedicated Ground Pin
         TDI  = Test Data In, JTAG pin
         TDO  = Test Data Out, JTAG pin
         TCK  = Test Clock, JTAG pin
         TMS  = Test Mode Select, JTAG pin
         PE   = Port Enable pin
  PROHIBITED  = User reserved pin
****************************  Compiler Options  ****************************

Following is a list of all global compiler options used by the fitter run.

Device(s) Specified                         : XC9572-7-PC84
Use Timing Constraints                      : ON
Use Design Location Constraints             : ON
Create Programmable Ground Pins             : OFF
Use Advanced Fitting                        : ON
Use Local Feedback                          : ON
Use Pin Feedback                            : ON
Default Power Setting                       : STD
Default Output Slew Rate                    : FAST
Guide File Used                             : NONE
Multi Level Logic Optimization              : ON
Timing Optimization                         : ON
Power/Slew Optimization                     : OFF
High Fitting Effort                         : ON
Automatic Wire-ANDing                       : ON
Xor Synthesis                               : ON
D/T Synthesis                               : ON
Use Boolean Minimization                    : ON
Global Clock(GCK) Optimization              : ON
Global Set/Reset(GSR) Optimization          : ON
Global Output Enable(GTS) Optimization      : ON
Collapsing pterm limit                      : 25
Collapsing input limit                      : 36
123

ex10.rpt - 源码说明

本页面展示了「[VHDL经典设计26例]--在xilinx芯片上调试通过--[01--1位全加器][02--2选1多路选择器][03--8位硬件加法器][04--7段数码显示译码器][05--8位串入并出寄存器][」中的 ex10.rpt 源码文件，采用 RPT 编程语言编写，共 629 行代码。您可以在线阅读完整代码内容，也可以返回资源详情页下载完整源码包进行本地学习和开发。

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