ex10.rpt
来自「[VHDL经典设计26例]--在xilinx芯片上调试通过--[01--1位全加」· RPT 代码 · 共 629 行 · 第 1/3 页
RPT
629 行
4: cout2.FBK.LFBK 10: "dout1<2>" 16: "dout3<0>"
5: "dout0<1>" 11: "dout1<3>" 17: "dout3<1>"
6: "dout0<2>" 12: "dout2<0>" 18: p_cnt_en.PIN
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
led0<1> ....X............X...................... 2 2
led0<2> .....X...........X...................... 2 2
led1<0> .......X.........X...................... 2 2
led0<3> ......X..........X...................... 2 2
led1<2> .........X.......X...................... 2 2
led1<1> ........X........X...................... 2 2
cout2 X.XX.......XXXX..X...................... 8 8
cout1 XXX....XXXX......X...................... 8 8
led1<3> ..........X......X...................... 2 2
led2<1> ............X....X...................... 2 2
led2<0> ...........X.....X...................... 2 2
led2<3> ..............X..X...................... 2 2
led3<1> ................XX...................... 2 2
led2<2> .............X...X...................... 2 2
led3<0> ...............X.X...................... 2 2
dout1<1> XX.....XXXX......X...................... 7 7
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK/FCLK - Global clock
O - Output GTS/FOE - Global 3state/output-enable
(b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB3 ***********************************
Number of function block inputs used/remaining: 0/36
Number of signals used by logic mapping into function block: 0
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB3_1 25 I/O
(unused) 0 0 0 5 FB3_2 17 I/O
(unused) 0 0 0 5 FB3_3 31 I/O
(unused) 0 0 0 5 FB3_4 32 I/O
(unused) 0 0 0 5 FB3_5 19 I/O
(unused) 0 0 0 5 FB3_6 34 I/O
(unused) 0 0 0 5 FB3_7 35 I/O
(unused) 0 0 0 5 FB3_8 21 I/O
(unused) 0 0 0 5 FB3_9 26 I/O
(unused) 0 0 0 5 FB3_10 40 I/O
(unused) 0 0 0 5 FB3_11 33 I/O
(unused) 0 0 0 5 FB3_12 41 I/O
(unused) 0 0 0 5 FB3_13 43 I/O
(unused) 0 0 0 5 FB3_14 36 I/O
(unused) 0 0 0 5 FB3_15 37 I/O
(unused) 0 0 0 5 FB3_16 45 I/O
(unused) 0 0 0 5 FB3_17 39 I/O
(unused) 0 0 0 5 FB3_18 (b)
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK/FCLK - Global clock
O - Output GTS/FOE - Global 3state/output-enable
(b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB4 ***********************************
Number of function block inputs used/remaining: 4/32
Number of signals used by logic mapping into function block: 4
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB4_1 46 I/O
(unused) 0 0 0 5 FB4_2 44 I/O
(unused) 0 0 0 5 FB4_3 51 I/O
p_cnt_en 1 0 0 4 FB4_4 STD 52 I/O I/O
(unused) 0 0 0 5 FB4_5 47 I/O
(unused) 0 0 0 5 FB4_6 54 I/O
(unused) 0 0 0 5 FB4_7 55 I/O
(unused) 0 0 0 5 FB4_8 48 I/O
(unused) 0 0 0 5 FB4_9 50 I/O
(unused) 0 0 0 5 FB4_10 57 I/O
(unused) 0 0 0 5 FB4_11 53 I/O
p_load 1 0 0 4 FB4_12 STD 58 I/O O
(unused) 0 0 0 5 FB4_13 61 I/O
p_rst_cnt 1 0 0 4 FB4_14 STD 56 I/O O
(unused) 0 0 0 5 FB4_15 65 I/O
dout0<0> 2 0 0 3 FB4_16 STD 62 I/O (b)
led0<0> 2 0 0 3 FB4_17 STD 66 I/O O
dout1<0> 3 0 0 2 FB4_18 STD (b) (b)
Signals Used by Logic in Function Block
1: clk1Hz 3: cout0 4: "dout0<0>.FBK".LFBK
2: N_p_cnt_en.FBK.LFBK
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
p_cnt_en .X...................................... 1 1
p_load .X...................................... 1 1
p_rst_cnt XX...................................... 2 2
dout0<0> XX...................................... 2 2
led0<0> .X.X.................................... 2 2
dout1<0> XXX..................................... 3 3
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK/FCLK - Global clock
O - Output GTS/FOE - Global 3state/output-enable
(b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
;;-----------------------------------------------------------------;;
; Implemented Equations.
p_load := N_p_cnt_en.FBK.LFBK
p_load.CLKF = clk1Hz ;FCLK/GCK
p_load.PRLD = VCC
"led0<0>" := "dout0<0>.FBK".LFBK
"led0<0>".CLKF = /N_p_cnt_en.FBK.LFBK
"led0<0>".PRLD = GND
"led0<1>" := "dout0<1>"
"led0<1>".CLKF = /p_cnt_en.PIN
"led0<1>".PRLD = GND
"led0<2>" := "dout0<2>"
"led0<2>".CLKF = /p_cnt_en.PIN
"led0<2>".PRLD = GND
"led0<3>" := "dout0<3>"
"led0<3>".CLKF = /p_cnt_en.PIN
"led0<3>".PRLD = GND
"led1<0>" := "dout1<0>"
"led1<0>".CLKF = /p_cnt_en.PIN
"led1<0>".PRLD = GND
"led1<1>" := "dout1<1>.FBK".LFBK
"led1<1>".CLKF = /p_cnt_en.PIN
"led1<1>".PRLD = GND
"led1<2>" := "dout1<2>"
"led1<2>".CLKF = /p_cnt_en.PIN
"led1<2>".PRLD = GND
"led1<3>" := "dout1<3>"
"led1<3>".CLKF = /p_cnt_en.PIN
"led1<3>".PRLD = GND
"led2<0>" := "dout2<0>"
"led2<0>".CLKF = /p_cnt_en.PIN
"led2<0>".PRLD = GND
"led2<1>" := "dout2<1>"
"led2<1>".CLKF = /p_cnt_en.PIN
"led2<1>".PRLD = GND
"led2<2>" := "dout2<2>"
"led2<2>".CLKF = /p_cnt_en.PIN
"led2<2>".PRLD = GND
"led2<3>" := "dout2<3>"
"led2<3>".CLKF = /p_cnt_en.PIN
"led2<3>".PRLD = GND
"led3<0>" := "dout3<0>"
"led3<0>".CLKF = /p_cnt_en.PIN
"led3<0>".PRLD = GND
"led3<1>" := "dout3<1>"
"led3<1>".CLKF = /p_cnt_en.PIN
"led3<1>".PRLD = GND
"led3<2>" := "dout3<2>.FBK".LFBK
"led3<2>".CLKF = /p_cnt_en.PIN
"led3<2>".PRLD = GND
"led3<3>" := "dout3<3>.FBK".LFBK
"led3<3>".CLKF = /p_cnt_en.PIN
"led3<3>".PRLD = GND
p_cnt_en := /N_p_cnt_en.FBK.LFBK
p_cnt_en.CLKF = clk1Hz ;FCLK/GCK
p_cnt_en.PRLD = GND
p_rst_cnt = /clk1Hz * /N_p_cnt_en.FBK.LFBK
cout0 := cout0.FBK.LFBK * /p_cnt_en.PIN
+ "dout0<0>" * /"dout0<2>.FBK".LFBK *
/"dout0<1>.FBK".LFBK * "dout0<3>.FBK".LFBK * p_cnt_en.PIN
cout0.CLKF = uclk ;FCLK/GCK
cout0.RSTF = /clk1Hz * /p_cnt_en.PIN
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