ex10.rpt
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RPT
629 行
cpldfit: version E.38 Xilinx Inc.
Fitter Report
Design Name: ex10 Date: 3-13-2008, 4:58PM
Device Used: XC9572-7-PC84
Fitting Status: Successful
**************************** Resource Summary ****************************
Macrocells Product Terms Registers Pins Function Block
Used Used Used Used Inputs Used
38 /72 ( 52%) 102 /360 ( 28%) 37 /72 ( 51%) 21 /69 ( 30%) 43 /144 ( 29%)
PIN RESOURCES:
Signal Type Required Mapped | Pin Type Used Remaining
------------------------------------|---------------------------------------
Input : 0 0 | I/O : 17 46
Output : 18 18 | GCK/IO : 2 1
Bidirectional : 1 1 | GTS/IO : 2 0
GCK : 2 2 | GSR/IO : 0 1
GTS : 0 0 |
GSR : 0 0 |
---- ----
Total 21 21
MACROCELL RESOURCES:
Total Macrocells Available 72
Registered Macrocells 37
Non-registered Macrocell driving I/O 1
GLOBAL RESOURCES:
Signal 'uclk' mapped onto global clock net GCK1.
Signal 'clk1Hz' mapped onto global clock net GCK2.
Global output enable net(s) unused.
Global set/reset net(s) unused.
POWER DATA:
There are 38 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
There are a total of 38 macrocells used (MC).
End of Resource Summary
***************Resources Used by Successfully Mapped Logic******************
** LOGIC **
Signal Total Signals Loc Pwr Slew Pin Pin Pin
Name Pt Used Mode Rate # Type Use
cout0 3 7 FB1_12 STD 18 I/O (b)
cout1 4 8 FB2_10 STD 75 I/O (b)
cout2 4 8 FB2_9 STD 74 GSR/I/O (b)
dout0<0> 2 2 FB4_16 STD 62 I/O (b)
dout0<1> 4 6 FB1_16 STD 23 I/O (b)
dout0<2> 2 4 FB1_4 STD 7 I/O (b)
dout0<3> 3 6 FB1_11 STD 10 GCK/I/O GCK/I
dout1<0> 3 3 FB4_18 STD (b) (b)
dout1<1> 5 7 FB2_18 STD (b) (b)
dout1<2> 3 5 FB1_10 STD 13 I/O (b)
dout1<3> 4 7 FB1_15 STD 14 I/O (b)
dout2<0> 3 3 FB1_9 STD 9 GCK/I/O GCK
dout2<1> 5 7 FB1_18 STD 24 I/O (b)
dout2<2> 3 5 FB1_8 STD 5 I/O (b)
dout2<3> 4 7 FB1_14 STD 12 GCK/I/O (b)
dout3<0> 3 3 FB1_7 STD 11 I/O (b)
dout3<1> 5 7 FB1_17 STD 15 I/O (b)
dout3<2> 3 5 FB1_6 STD 3 I/O (b)
dout3<3> 4 7 FB1_13 STD 20 I/O (b)
led0<0> 2 2 FB4_17 STD FAST 66 I/O O
led0<1> 2 2 FB2_2 STD FAST 69 I/O O
led0<2> 2 2 FB2_4 STD FAST 68 I/O O
led0<3> 2 2 FB2_6 STD FAST 71 I/O O
led1<0> 2 2 FB2_5 STD FAST 70 I/O O
led1<1> 2 2 FB2_8 STD FAST 72 I/O O
led1<2> 2 2 FB2_7 STD FAST 76 GTS/I/O O
led1<3> 2 2 FB2_11 STD FAST 77 GTS/I/O O
led2<0> 2 2 FB2_13 STD FAST 80 I/O O
led2<1> 2 2 FB2_12 STD FAST 79 I/O O
led2<2> 2 2 FB2_16 STD FAST 82 I/O O
led2<3> 2 2 FB2_14 STD FAST 81 I/O O
led3<0> 2 2 FB2_17 STD FAST 84 I/O O
led3<1> 2 2 FB2_15 STD FAST 83 I/O O
led3<2> 2 2 FB1_5 STD FAST 2 I/O O
led3<3> 2 2 FB1_1 STD FAST 4 I/O O
p_cnt_en 1 1 FB4_4 STD FAST 52 I/O I/O
p_load 1 1 FB4_12 STD FAST 58 I/O O
p_rst_cnt 1 2 FB4_14 STD FAST 56 I/O O
** INPUTS **
Signal Loc Pin Pin Pin
Name # Type Use
clk1Hz FB1_11 10 GCK/I/O GCK/I
uclk FB1_9 9 GCK/I/O GCK
End of Resources Used by Successfully Mapped Logic
*********************Function Block Resource Summary***********************
Function # of FB Inputs Signals Total O/IO IO
Block Macrocells Used Used Pt Used Req Avail
FB1 16 21 21 53 2/0 18
FB2 16 18 18 39 13/0 17
FB3 0 0 0 0 0/0 17
FB4 6 4 4 10 3/1 17
---- ----- ----- -----
38 102 18/1 69
*********************************** FB1 ***********************************
Number of function block inputs used/remaining: 21/15
Number of signals used by logic mapping into function block: 21
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
led3<3> 2 0 0 3 FB1_1 STD 4 I/O O
(unused) 0 0 0 5 FB1_2 1 I/O
(unused) 0 0 0 5 FB1_3 6 I/O
dout0<2> 2 0 0 3 FB1_4 STD 7 I/O (b)
led3<2> 2 0 0 3 FB1_5 STD 2 I/O O
dout3<2> 3 0 0 2 FB1_6 STD 3 I/O (b)
dout3<0> 3 0 0 2 FB1_7 STD 11 I/O (b)
dout2<2> 3 0 0 2 FB1_8 STD 5 I/O (b)
dout2<0> 3 0 0 2 FB1_9 STD 9 GCK/I/O GCK
dout1<2> 3 0 0 2 FB1_10 STD 13 I/O (b)
dout0<3> 3 0 0 2 FB1_11 STD 10 GCK/I/O GCK/I
cout0 3 0 0 2 FB1_12 STD 18 I/O (b)
dout3<3> 4 0 0 1 FB1_13 STD 20 I/O (b)
dout2<3> 4 0 0 1 FB1_14 STD 12 GCK/I/O (b)
dout1<3> 4 0 0 1 FB1_15 STD 14 I/O (b)
dout0<1> 4 0 0 1 FB1_16 STD 23 I/O (b)
dout3<1> 5 0 0 0 FB1_17 STD 15 I/O (b)
dout2<1> 5 0 0 0 FB1_18 STD 24 I/O (b)
Signals Used by Logic in Function Block
1: clk1Hz 8: "dout0<3>.FBK".LFBK
15: "dout2<2>.FBK".LFBK
2: cout0.FBK.LFBK 9: "dout1<0>" 16: "dout2<3>.FBK".LFBK
3: cout1 10: "dout1<1>" 17: "dout3<0>.FBK".LFBK
4: cout2 11: "dout1<2>.FBK".LFBK
18: "dout3<1>.FBK".LFBK
5: "dout0<0>" 12: "dout1<3>.FBK".LFBK
19: "dout3<2>.FBK".LFBK
6: "dout0<1>.FBK".LFBK
13: "dout2<0>.FBK".LFBK
20: "dout3<3>.FBK".LFBK
7: "dout0<2>.FBK".LFBK
14: "dout2<1>.FBK".LFBK
21: p_cnt_en.PIN
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
led3<3> ...................XX................... 2 2
dout0<2> X...XX..............X................... 4 4
led3<2> ..................X.X................... 2 2
dout3<2> X..X............XX..X................... 5 5
dout3<0> X..X................X................... 3 3
dout2<2> X.X.........XX......X................... 5 5
dout2<0> X.X.................X................... 3 3
dout1<2> XX......XX..........X................... 5 5
dout0<3> X...XXXX............X................... 6 6
cout0 XX..XXXX............X................... 7 7
dout3<3> X..X............XXXXX................... 7 7
dout2<3> X.X.........XXXX....X................... 7 7
dout1<3> XX......XXXX........X................... 7 7
dout0<1> X...XXXX............X................... 6 6
dout3<1> X..X............XXXXX................... 7 7
dout2<1> X.X.........XXXX....X................... 7 7
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK/FCLK - Global clock
O - Output GTS/FOE - Global 3state/output-enable
(b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB2 ***********************************
Number of function block inputs used/remaining: 18/18
Number of signals used by logic mapping into function block: 18
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB2_1 63 I/O
led0<1> 2 0 0 3 FB2_2 STD 69 I/O O
(unused) 0 0 0 5 FB2_3 67 I/O
led0<2> 2 0 0 3 FB2_4 STD 68 I/O O
led1<0> 2 0 0 3 FB2_5 STD 70 I/O O
led0<3> 2 0 0 3 FB2_6 STD 71 I/O O
led1<2> 2 0 0 3 FB2_7 STD 76 GTS/I/O O
led1<1> 2 0 0 3 FB2_8 STD 72 I/O O
cout2 4 0 0 1 FB2_9 STD 74 GSR/I/O (b)
cout1 4 0 0 1 FB2_10 STD 75 I/O (b)
led1<3> 2 0 0 3 FB2_11 STD 77 GTS/I/O O
led2<1> 2 0 0 3 FB2_12 STD 79 I/O O
led2<0> 2 0 0 3 FB2_13 STD 80 I/O O
led2<3> 2 0 0 3 FB2_14 STD 81 I/O O
led3<1> 2 0 0 3 FB2_15 STD 83 I/O O
led2<2> 2 0 0 3 FB2_16 STD 82 I/O O
led3<0> 2 0 0 3 FB2_17 STD 84 I/O O
dout1<1> 5 0 0 0 FB2_18 STD (b) (b)
Signals Used by Logic in Function Block
1: clk1Hz 7: "dout0<3>" 13: "dout2<1>"
2: cout0 8: "dout1<0>" 14: "dout2<2>"
3: cout1.FBK.LFBK 9: "dout1<1>.FBK".LFBK
15: "dout2<3>"
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