ex10.tim

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                           Performance Summary Report
                           --------------------------

Design:     ex10
Device:     XC9572-7-PC84
Speed File: Version 3.0
Program:    Timing Report Generator:  version E.38
Date:       Thu Mar 13 16:58:38 2008

Performance Summary: 

Pad to Pad (tPD)                          :          7.5ns (1 macrocell levels)
Pad 'clk1Hz' to Pad 'p_rst_cnt'                                   

Clock net 'p_cnt_en.Q' path delays:

                          Minimum Clock Period: 10.0ns
                     Maximum Internal Clock Speed: 100.0Mhz
                         (Limited by Clock Pulse Width)

Clock net 'clk1Hz' path delays:

Clock Pad to Output Pad (tCO)             :         13.0ns (1 macrocell levels)
Clock Pad 'clk1Hz' to Output Pad 'led0<1>'                                (GCK)

Clock to Setup (tCYC)                     :          8.0ns (1 macrocell levels)
Clock to Q, net 'p_cnt_en.Q' to DFF Setup(D) at 'p_cnt_en.D'              (GCK)
Target FF drives output net 'N_p_cnt_en$Q'

                          Minimum Clock Period: 8.0ns
                     Maximum Internal Clock Speed: 125.0Mhz
                         (Limited by Clock Pulse Width)

Clock net 'cout2.Q' path delays:

Clock to Setup (tCYC)                     :          8.0ns (1 macrocell levels)
Clock to Q, net 'dout3<0>.Q' to TFF Setup(D) at 'dout3<2>.D'      (Pterm Clock)

                          Minimum Clock Period: 10.0ns
                     Maximum Internal Clock Speed: 100.0Mhz
                         (Limited by Clock Pulse Width)

Clock net 'cout1.Q' path delays:

Clock to Setup (tCYC)                     :         12.0ns (1 macrocell levels)
Clock to Q, net 'dout2<0>.Q' to DFF Setup(D) at 'cout2.D'         (Pterm Clock)
Target FF drives output net 'cout2'

                          Minimum Clock Period: 12.0ns
                     Maximum Internal Clock Speed: 83.3Mhz
                            (Limited by Cycle Time)

Clock net 'cout0.Q' path delays:

Clock to Setup (tCYC)                     :         12.0ns (1 macrocell levels)
Clock to Q, net 'dout1<0>.Q' to DFF Setup(D) at 'cout1.D'         (Pterm Clock)
Target FF drives output net 'cout1'

                          Minimum Clock Period: 12.0ns
                     Maximum Internal Clock Speed: 83.3Mhz
                            (Limited by Cycle Time)

Clock net 'uclk' path delays:

Clock to Setup (tCYC)                     :         12.0ns (1 macrocell levels)
Clock to Q, net 'dout0<0>.Q' to DFF Setup(D) at 'cout0.D'                 (GCK)
Target FF drives output net 'cout0'

                          Minimum Clock Period: 12.0ns
                     Maximum Internal Clock Speed: 83.3Mhz
                            (Limited by Cycle Time)

--------------------------------------------------------------------------------
                            Pad to Pad (tPD) (nsec)

\ From        c
 \            l
  \           k
   \          1
    \         H
     \        z
      \        
       \       
        \      
  To     \------

p_rst_cnt   7.5

--------------------------------------------------------------------------------
                      Clock Pad to Output Pad (tCO) (nsec)

\ From        c
 \            l
  \           k
   \          1
    \         H
     \        z
      \        
       \       
        \      
  To     \------

led0<0>    12.0
led0<1>    13.0
led0<2>    13.0
led0<3>    13.0
led1<0>    13.0
led1<1>    13.0
led1<2>    13.0
led1<3>    13.0
led2<0>    13.0
led2<1>    13.0
led2<2>    13.0
led2<3>    13.0
led3<0>    13.0
led3<1>    13.0
led3<2>    13.0
led3<3>    13.0
p_cnt_en    4.5
p_load      4.5
p_rst_cnt  11.0

--------------------------------------------------------------------------------
                          Clock to Setup (tCYC) (nsec)
                                (Clock: clk1Hz)

\ From         p
 \             _
  \            c
   \           n
    \          t
     \         _
      \        e
       \       n
        \      .
         \     Q
  To      \------

p_cnt_en.D   8.0
p_load.D     8.0

--------------------------------------------------------------------------------
                          Clock to Setup (tCYC) (nsec)
                                (Clock: cout2.Q)

\ From         d     d     d     d
 \             o     o     o     o
  \            u     u     u     u
   \           t     t     t     t
    \          3     3     3     3
     \         <     <     <     <
      \        0     1     2     3
       \       >     >     >     >
        \      .     .     .     .
         \     Q     Q     Q     Q
  To      \------------------------

dout3<1>.D   8.0   8.0   8.0   8.0
dout3<2>.D   8.0   8.0            
dout3<3>.D   8.0   8.0   8.0   8.0

--------------------------------------------------------------------------------
                          Clock to Setup (tCYC) (nsec)
                                (Clock: cout1.Q)

\ From         c     d     d     d     d
 \             o     o     o     o     o
  \            u     u     u     u     u
   \           t     t     t     t     t
    \          2     2     2     2     2
     \         .     <     <     <     <
      \        Q     0     1     2     3
       \             >     >     >     >
        \            .     .     .     .
         \           Q     Q     Q     Q
  To      \------------------------------

cout2.D      8.0  12.0  12.0  12.0  12.0
dout2<1>.D         8.0   8.0   8.0   8.0
dout2<2>.D         8.0   8.0            
dout2<3>.D         8.0   8.0   8.0   8.0

--------------------------------------------------------------------------------
                          Clock to Setup (tCYC) (nsec)
                                (Clock: cout0.Q)

\ From         c     d     d     d     d
 \             o     o     o     o     o
  \            u     u     u     u     u
   \           t     t     t     t     t
    \          1     1     1     1     1
     \         .     <     <     <     <
      \        Q     0     1     2     3
       \             >     >     >     >
        \            .     .     .     .
         \           Q     Q     Q     Q
  To      \------------------------------

cout1.D      8.0  12.0   8.0  12.0  12.0
dout1<1>.D        12.0   8.0  12.0  12.0
dout1<2>.D        12.0  12.0            
dout1<3>.D        12.0  12.0   8.0   8.0

--------------------------------------------------------------------------------
                          Clock to Setup (tCYC) (nsec)
                                 (Clock: uclk)

\ From         c     d     d     d     d
 \             o     o     o     o     o
  \            u     u     u     u     u
   \           t     t     t     t     t
    \          0     0     0     0     0
     \         .     <     <     <     <
      \        Q     0     1     2     3
       \             >     >     >     >
        \            .     .     .     .
         \           Q     Q     Q     Q
  To      \------------------------------

cout0.D      8.0  12.0   8.0   8.0   8.0
dout0<1>.D        12.0   8.0   8.0   8.0
dout0<2>.D        12.0   8.0            
dout0<3>.D        12.0   8.0   8.0   8.0

Path Type Definition: 

Pad to Pad (tPD) -                        Reports pad to pad paths that start 
                                          at input pads and end at output pads. 
                                          Paths are not traced through 
                                          registers. 

Clock Pad to Output Pad (tCO) -           Reports paths that start at input 
                                          pads trace through clock inputs of 
                                          registers and end at output pads. 
                                          Paths are not traced through PRE/CLR 
                                          inputs of registers. 

Setup to Clock at Pad (tSU) -             Reports external setup time of data 
                                          to clock at pad. Data path starts at 
                                          an input pad and end at register D/T 
                                          input. Clock path starts at input pad 
                                          and ends at the register clock input. 
                                          Paths are not traced through 
                                          registers. 

Clock to Setup (tCYC) -                   Register to register cycle time. 
                                          Include source register tCO and 
                                          destination register tSU.