ex10.mod

来自「[VHDL经典设计26例]--在xilinx芯片上调试通过--[01--1位全加」· MOD 代码 · 共 53 行

MODEL
MODEL_VERSION "v1998.8";
DESIGN "ex10";

/* port names and type */
INPUT S:PIN9 = uclk;
INPUT S:PIN10 = clk1Hz;
OUTPUT S:PIN52 = p_cnt_en;
OUTPUT S:PIN56 = p_rst_cnt;
OUTPUT S:PIN66 = led0<0>;
OUTPUT S:PIN69 = led0<1>;
OUTPUT S:PIN68 = led0<2>;
OUTPUT S:PIN71 = led0<3>;
OUTPUT S:PIN70 = led1<0>;
OUTPUT S:PIN72 = led1<1>;
OUTPUT S:PIN76 = led1<2>;
OUTPUT S:PIN77 = led1<3>;
OUTPUT S:PIN80 = led2<0>;
OUTPUT S:PIN79 = led2<1>;
OUTPUT S:PIN82 = led2<2>;
OUTPUT S:PIN81 = led2<3>;
OUTPUT S:PIN84 = led3<0>;
OUTPUT S:PIN83 = led3<1>;
OUTPUT S:PIN2 = led3<2>;
OUTPUT S:PIN4 = led3<3>;
OUTPUT S:PIN58 = p_load;

/* timing arc definitions */
clk1Hz_p_rst_cnt_delay: DELAY clk1Hz p_rst_cnt;
clk1Hz_p_cnt_en_delay: DELAY clk1Hz p_cnt_en;
clk1Hz_p_rst_cnt_delay: DELAY clk1Hz p_rst_cnt;
clk1Hz_led0<0>_delay: DELAY clk1Hz led0<0>;
clk1Hz_led0<1>_delay: DELAY clk1Hz led0<1>;
clk1Hz_led0<2>_delay: DELAY clk1Hz led0<2>;
clk1Hz_led0<3>_delay: DELAY clk1Hz led0<3>;
clk1Hz_led1<0>_delay: DELAY clk1Hz led1<0>;
clk1Hz_led1<1>_delay: DELAY clk1Hz led1<1>;
clk1Hz_led1<2>_delay: DELAY clk1Hz led1<2>;
clk1Hz_led1<3>_delay: DELAY clk1Hz led1<3>;
clk1Hz_led2<0>_delay: DELAY clk1Hz led2<0>;
clk1Hz_led2<1>_delay: DELAY clk1Hz led2<1>;
clk1Hz_led2<2>_delay: DELAY clk1Hz led2<2>;
clk1Hz_led2<3>_delay: DELAY clk1Hz led2<3>;
clk1Hz_led3<0>_delay: DELAY clk1Hz led3<0>;
clk1Hz_led3<1>_delay: DELAY clk1Hz led3<1>;
clk1Hz_led3<2>_delay: DELAY clk1Hz led3<2>;
clk1Hz_led3<3>_delay: DELAY clk1Hz led3<3>;
clk1Hz_p_load_delay: DELAY clk1Hz p_load;

/* timing check arc definitions */

ENDMODEL