time_sim.edn

来自「[VHDL经典设计26例]--在xilinx芯片上调试通过--[01--1位全加」· EDN 代码 · 共 1,543 行 · 第 1/5 页

(edif ex10
  (edifVersion 2 0 0)
  (edifLevel 0)
  (keywordMap (keywordLevel 0))
  (status
    (written
      (timestamp 2008 3 13 16 58 40)
      (program "Xilinx ngd2edif" (version "E.38"))
      (comment "Command line: -w -v fndtn ex10.nga time_sim.edn ")))
  (external SIMPRIMS
    (edifLevel 0)
    (technology (numberDefinition
      (scale 1 (E 1 -12) (unit TIME))))
    (cell x_opad
      (cellType GENERIC)
        (view view_1
          (viewType NETLIST)
          (interface
            (port PAD
              (direction OUTPUT)
            )
          )
      )
    )
    (cell x_buf
      (cellType GENERIC)
        (view view_1
          (viewType NETLIST)
          (interface
            (port IN
              (direction INPUT)
            )
            (port OUT
              (direction OUTPUT)
            )
          )
      )
    )
    (cell x_ff
      (cellType GENERIC)
        (view view_1
          (viewType NETLIST)
          (interface
            (port IN
              (direction INPUT)
            )
            (port CE
              (direction INPUT)
            )
            (port CLK
              (direction INPUT)
            )
            (port SET
              (direction INPUT)
            )
            (port RST
              (direction INPUT)
            )
            (port OUT
              (direction OUTPUT)
            )
          )
      )
    )
    (cell x_one
      (cellType GENERIC)
        (view view_1
          (viewType NETLIST)
          (interface
            (port OUT
              (direction OUTPUT)
            )
          )
      )
    )
    (cell x_zero
      (cellType GENERIC)
        (view view_1
          (viewType NETLIST)
          (interface
            (port OUT
              (direction OUTPUT)
            )
          )
      )
    )
    (cell x_or2
      (cellType GENERIC)
        (view view_1
          (viewType NETLIST)
          (interface
            (port IN0
              (direction INPUT)
            )
            (port IN1
              (direction INPUT)
            )
            (port OUT
              (direction OUTPUT)
            )
          )
      )
    )
    (cell x_and2
      (cellType GENERIC)
        (view view_1
          (viewType NETLIST)
          (interface
            (port IN0
              (direction INPUT)
            )
            (port IN1
              (direction INPUT)
            )
            (port OUT
              (direction OUTPUT)
            )
          )
      )
    )
    (cell x_xor2
      (cellType GENERIC)
        (view view_1
          (viewType NETLIST)
          (interface
            (port IN0
              (direction INPUT)
            )
            (port IN1
              (direction INPUT)
            )
            (port OUT
              (direction OUTPUT)
            )
          )
      )
    )
    (cell x_ipad
      (cellType GENERIC)
        (view view_1
          (viewType NETLIST)
          (interface
            (port PAD
              (direction INPUT)
            )
          )
      )
    )
    (cell x_and3
      (cellType GENERIC)
        (view view_1
          (viewType NETLIST)
          (interface
            (port IN0
              (direction INPUT)
            )
            (port IN1
              (direction INPUT)
            )
            (port IN2
              (direction INPUT)
            )
            (port OUT
              (direction OUTPUT)
            )
          )
      )
    )
    (cell x_or3
      (cellType GENERIC)
        (view view_1
          (viewType NETLIST)
          (interface
            (port IN0
              (direction INPUT)
            )
            (port IN1
              (direction INPUT)
            )
            (port IN2
              (direction INPUT)
            )
            (port OUT
              (direction OUTPUT)
            )
          )
      )
    )
    (cell x_and4
      (cellType GENERIC)
        (view view_1
          (viewType NETLIST)
          (interface
            (port IN0
              (direction INPUT)
            )
            (port IN1
              (direction INPUT)
            )
            (port IN2
              (direction INPUT)
            )
            (port IN3
              (direction INPUT)
            )
            (port OUT
              (direction OUTPUT)
            )
          )
      )
    )
    (cell x_and5
      (cellType GENERIC)
        (view view_1
          (viewType NETLIST)
          (interface
            (port IN0
              (direction INPUT)
            )
            (port IN1
              (direction INPUT)
            )
            (port IN2
              (direction INPUT)
            )
            (port IN3
              (direction INPUT)
            )
            (port IN4
              (direction INPUT)
            )
            (port OUT
              (direction OUTPUT)
            )
          )
      )
    )
    (cell x_inv
      (cellType GENERIC)
        (view view_1
          (viewType NETLIST)
          (interface
            (port IN
              (direction INPUT)
            )
            (port OUT
              (direction OUTPUT)
            )
          )
      )
    )
  )

  (library ex10_lib
    (edifLevel 0)
    (technology (numberDefinition
      (scale 1 (E 1 -12) (unit TIME))))
    (cell ex10
      (cellType GENERIC)
        (view view_1
          (viewType NETLIST)
          (interface
            (port uclk
              (direction INPUT)
              (designator "9")
            )
            (port clk1Hz
              (direction INPUT)
              (designator "10")
            )
            (port p_load
              (direction OUTPUT)
              (designator "58")
            )
            (port p_cnt_en
              (direction OUTPUT)
              (designator "52")
            )
            (port p_rst_cnt
              (direction OUTPUT)
              (designator "56")
            )
            (port (rename led0_0__ "led0<0>")
              (direction OUTPUT)
              (designator "66")
            )
            (port (rename led0_1__ "led0<1>")
              (direction OUTPUT)
              (designator "69")
            )
            (port (rename led0_2__ "led0<2>")
              (direction OUTPUT)
              (designator "68")
            )
            (port (rename led0_3__ "led0<3>")
              (direction OUTPUT)
              (designator "71")
            )
            (port (rename led1_0__ "led1<0>")
              (direction OUTPUT)
              (designator "70")
            )
            (port (rename led1_1__ "led1<1>")
              (direction OUTPUT)
              (designator "72")
            )
            (port (rename led1_2__ "led1<2>")
              (direction OUTPUT)
              (designator "76")