ex12.out

来自「[VHDL经典设计26例]--在xilinx芯片上调试通过--[01--1位全加」· OUT 代码 · 共 37 行

Reading in the Synopsys vhdl primitives.
Warning: Variable 'clr' is being read 
	in routine EX12 line 17 in file 'D:/temp/eda6000/xc95/ex12/ex12.vhd', 
	but is not in the process sensitivity list of the block which begins 
	there.   (HDL-179)

Inferred memory devices in process 
	in routine EX12 line 17 in file
         'D:/temp/eda6000/xc95/ex12/ex12.vhd'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|        q_reg        | Flip-flop |   4   |  N  | N  | ?  | ?  | ?  | ?  | ?  |
===============================================================================

q_reg<0>
--------
    Async-reset: clr


q_reg<2>
--------
    Async-reset: clr


q_reg<3>
--------
    Async-reset: clr


q_reg<1>
--------
    Async-reset: clr


Writing to hnl file 'd:\temp\EDA6000\XC95\EX12\ex12/workdirs/WORK/EX12.hnl'