ex12.mfd

来自「[VHDL经典设计26例]--在xilinx芯片上调试通过--[01--1位全加」· MFD 代码 · 共 202 行
MFD
202 行
MDF Database:  version 1.0
MDF_INFO | ex12 | XC9572-7-PC84
MACROCELL | 3 | 11 | N37
ATTRIBUTES | 396034 | 0
INPUTS | 4 | q<0>.FBK".LFBK  | q<2>.FBK".LFBK  | q<3>.FBK".LFBK  | q<1>.FBK".LFBK
INPUTMC | 4 | 3 | 0 | 3 | 14 | 3 | 1 | 3 | 16
EQ | 2 | 
   /"err<2>"  =  /"q<1>.FBK".LFBK * /"q<0>.FBK".LFBK * 
	/"q<2>.FBK".LFBK * "q<3>.FBK".LFBK

MACROCELL | 3 | 16 | q<1>
ATTRIBUTES | 8586032 | 0
OUTPUTMC | 8 | 3 | 11 | 3 | 16 | 3 | 0 | 3 | 14 | 3 | 1 | 3 | 13 | 3 | 15 | 3 | 17
INPUTS | 10 | q<0>.FBK".LFBK  | q<2>.FBK".LFBK  | q<3>.FBK".LFBK  | din  | d<1>  | d<2>  | EXP0_.EXP  | q<1>.FBK".LFBK  | clk  | clr
INPUTMC | 5 | 3 | 0 | 3 | 14 | 3 | 1 | 3 | 15 | 3 | 16
INPUTP | 5 | 46 | 35 | 36 | 49 | 48
IMPORTS | 1 | 3 | 15
EQ | 20 | 
    "q<1>"  :=  din * "d<1>" * "q<1>.FBK".LFBK * 
	/"q<0>.FBK".LFBK * "q<2>.FBK".LFBK * /"q<3>.FBK".LFBK
	+ din * "d<2>" * /"q<1>.FBK".LFBK * 
	"q<0>.FBK".LFBK * "q<2>.FBK".LFBK * /"q<3>.FBK".LFBK
	+ /din * /"d<1>" * "q<1>.FBK".LFBK * 
	/"q<0>.FBK".LFBK * "q<2>.FBK".LFBK * /"q<3>.FBK".LFBK
;Imported pterms FB4_16
	+ din * "d<6>" * /"q<1>.FBK".LFBK * 
	"q<0>.FBK".LFBK * /"q<2>.FBK".LFBK * /"q<3>.FBK".LFBK
	+ din * "d<5>" * "q<1>.FBK".LFBK * 
	/"q<0>.FBK".LFBK * /"q<2>.FBK".LFBK * /"q<3>.FBK".LFBK
	+ /din * /"d<6>" * /"q<1>.FBK".LFBK * 
	"q<0>.FBK".LFBK * /"q<2>.FBK".LFBK * /"q<3>.FBK".LFBK
	+ /din * /"d<5>" * "q<1>.FBK".LFBK * 
	/"q<0>.FBK".LFBK * /"q<2>.FBK".LFBK * /"q<3>.FBK".LFBK
	+ /din * /"d<2>" * /"q<1>.FBK".LFBK * 
	"q<0>.FBK".LFBK * "q<2>.FBK".LFBK * /"q<3>.FBK".LFBK
    "q<1>".CLKF  =  clk
    "q<1>".RSTF  =  clr
    "q<1>".PRLD  =  GND

MACROCELL | 3 | 0 | q<0>
ATTRIBUTES | 8586032 | 0
OUTPUTMC | 8 | 3 | 11 | 3 | 16 | 3 | 0 | 3 | 14 | 3 | 1 | 3 | 13 | 3 | 15 | 3 | 17
INPUTS | 10 | q<0>.FBK".LFBK  | q<2>.FBK".LFBK  | q<3>.FBK".LFBK  | din  | d<1>  | d<3>  | EXP1_.EXP  | q<1>.FBK".LFBK  | clk  | clr
INPUTMC | 5 | 3 | 0 | 3 | 14 | 3 | 1 | 3 | 17 | 3 | 16
INPUTP | 5 | 46 | 35 | 37 | 49 | 48
IMPORTS | 1 | 3 | 17
EQ | 20 | 
    "q<0>"  :=  din * "d<1>" * "q<1>.FBK".LFBK * 
	/"q<0>.FBK".LFBK * "q<2>.FBK".LFBK * /"q<3>.FBK".LFBK
	+ din * "d<3>" * /"q<1>.FBK".LFBK * 
	/"q<0>.FBK".LFBK * "q<2>.FBK".LFBK * /"q<3>.FBK".LFBK
	+ /din * /"d<1>" * "q<1>.FBK".LFBK * 
	/"q<0>.FBK".LFBK * "q<2>.FBK".LFBK * /"q<3>.FBK".LFBK
;Imported pterms FB4_18
	+ din * "d<7>" * /"q<1>.FBK".LFBK * 
	/"q<0>.FBK".LFBK * /"q<2>.FBK".LFBK * /"q<3>.FBK".LFBK
	+ din * "d<5>" * "q<1>.FBK".LFBK * 
	/"q<0>.FBK".LFBK * /"q<2>.FBK".LFBK * /"q<3>.FBK".LFBK
	+ /din * /"d<7>" * /"q<1>.FBK".LFBK * 
	/"q<0>.FBK".LFBK * /"q<2>.FBK".LFBK * /"q<3>.FBK".LFBK
	+ /din * /"d<3>" * /"q<1>.FBK".LFBK * 
	/"q<0>.FBK".LFBK * "q<2>.FBK".LFBK * /"q<3>.FBK".LFBK
	+ /din * /"d<5>" * "q<1>.FBK".LFBK * 
	/"q<0>.FBK".LFBK * /"q<2>.FBK".LFBK * /"q<3>.FBK".LFBK
    "q<0>".CLKF  =  clk
    "q<0>".RSTF  =  clr
    "q<0>".PRLD  =  GND

MACROCELL | 3 | 14 | q<2>
ATTRIBUTES | 8586032 | 0
OUTPUTMC | 8 | 3 | 11 | 3 | 16 | 3 | 0 | 3 | 14 | 3 | 1 | 3 | 13 | 3 | 15 | 3 | 17
INPUTS | 10 | q<0>.FBK".LFBK  | q<2>.FBK".LFBK  | q<3>.FBK".LFBK  | din  | d<1>  | d<4>  | N_err<0>.EXP  | q<1>.FBK".LFBK  | clk  | clr
INPUTMC | 5 | 3 | 0 | 3 | 14 | 3 | 1 | 3 | 13 | 3 | 16
INPUTP | 5 | 46 | 35 | 38 | 49 | 48
IMPORTS | 1 | 3 | 13
EQ | 20 | 
    "q<2>"  :=  din * "d<1>" * "q<1>.FBK".LFBK * 
	/"q<0>.FBK".LFBK * "q<2>.FBK".LFBK * /"q<3>.FBK".LFBK
	+ din * "d<4>" * "q<1>.FBK".LFBK * 
	"q<0>.FBK".LFBK * /"q<2>.FBK".LFBK * /"q<3>.FBK".LFBK
	+ /din * /"d<1>" * "q<1>.FBK".LFBK * 
	/"q<0>.FBK".LFBK * "q<2>.FBK".LFBK * /"q<3>.FBK".LFBK
;Imported pterms FB4_14
	+ din * "d<3>" * /"q<1>.FBK".LFBK * 
	/"q<0>.FBK".LFBK * "q<2>.FBK".LFBK * /"q<3>.FBK".LFBK
	+ din * "d<2>" * /"q<1>.FBK".LFBK * 
	"q<0>.FBK".LFBK * "q<2>.FBK".LFBK * /"q<3>.FBK".LFBK
	+ /din * /"d<3>" * /"q<1>.FBK".LFBK * 
	/"q<0>.FBK".LFBK * "q<2>.FBK".LFBK * /"q<3>.FBK".LFBK
	+ /din * /"d<4>" * "q<1>.FBK".LFBK * 
	"q<0>.FBK".LFBK * /"q<2>.FBK".LFBK * /"q<3>.FBK".LFBK
	+ /din * /"d<2>" * /"q<1>.FBK".LFBK * 
	"q<0>.FBK".LFBK * "q<2>.FBK".LFBK * /"q<3>.FBK".LFBK
    "q<2>".CLKF  =  clk
    "q<2>".RSTF  =  clr
    "q<2>".PRLD  =  GND

MACROCELL | 3 | 1 | q<3>
ATTRIBUTES | 8586032 | 0
OUTPUTMC | 8 | 3 | 11 | 3 | 16 | 3 | 0 | 3 | 14 | 3 | 1 | 3 | 13 | 3 | 15 | 3 | 17
INPUTS | 8 | q<0>.FBK".LFBK  | q<2>.FBK".LFBK  | q<3>.FBK".LFBK  | din  | d<0>  | clk  | clr  | q<1>.FBK".LFBK
INPUTMC | 4 | 3 | 0 | 3 | 14 | 3 | 1 | 3 | 16
INPUTP | 4 | 46 | 32 | 49 | 48
EQ | 7 | 
    "q<3>"  :=  din * "d<0>" * "q<1>.FBK".LFBK * 
	"q<0>.FBK".LFBK * "q<2>.FBK".LFBK * /"q<3>.FBK".LFBK
	+ /din * /"d<0>" * "q<1>.FBK".LFBK * 
	"q<0>.FBK".LFBK * "q<2>.FBK".LFBK * /"q<3>.FBK".LFBK
    "q<3>".CLKF  =  clk
    "q<3>".RSTF  =  clr
    "q<3>".PRLD  =  GND

MACROCELL | 3 | 13 | N_err<0>
ATTRIBUTES | 396034 | 0
OUTPUTMC | 1 | 3 | 14
INPUTS | 9 | q<0>.FBK".LFBK  | q<2>.FBK".LFBK  | q<3>.FBK".LFBK  | din  | d<4>  | d<2>  | d<3>  | N_err<3>.EXP  | q<1>.FBK".LFBK
INPUTMC | 5 | 3 | 0 | 3 | 14 | 3 | 1 | 3 | 12 | 3 | 16
INPUTP | 4 | 46 | 38 | 36 | 37
EXPORTS | 1 | 3 | 14
IMPORTS | 1 | 3 | 12
EQ | 11 | 
    "err<0>"  =  ;Imported pterms FB4_13
    N_err<0>.EXP  =  din * "d<3>" * /"q<1>.FBK".LFBK * 
	/"q<0>.FBK".LFBK * "q<2>.FBK".LFBK * /"q<3>.FBK".LFBK
	+ din * "d<2>" * /"q<1>.FBK".LFBK * 
	"q<0>.FBK".LFBK * "q<2>.FBK".LFBK * /"q<3>.FBK".LFBK
	+ /din * /"d<3>" * /"q<1>.FBK".LFBK * 
	/"q<0>.FBK".LFBK * "q<2>.FBK".LFBK * /"q<3>.FBK".LFBK
	+ /din * /"d<4>" * "q<1>.FBK".LFBK * 
	"q<0>.FBK".LFBK * /"q<2>.FBK".LFBK * /"q<3>.FBK".LFBK
	+ /din * /"d<2>" * /"q<1>.FBK".LFBK * 
	"q<0>.FBK".LFBK * "q<2>.FBK".LFBK * /"q<3>.FBK".LFBK

MACROCELL | 3 | 12 | N_err<3>
ATTRIBUTES | 396034 | 0
OUTPUTMC | 1 | 3 | 13
INPUTS | 0
EXPORTS | 1 | 3 | 13
EQ | 2 | 
    "err<3>"  =  Vcc
    N_err<3>.EXP  =

MACROCELL | 3 | 3 | N_err<3>$BUF0
ATTRIBUTES | 396034 | 0
INPUTS | 0
EQ | 1 | 
    "err<1>"  =  Vcc

MACROCELL | 3 | 15 | EXP0_
ATTRIBUTES | 2048 | 0
OUTPUTMC | 1 | 3 | 16
INPUTS | 8 | q<0>.FBK".LFBK  | q<2>.FBK".LFBK  | q<3>.FBK".LFBK  | din  | d<5>  | d<2>  | d<6>  | q<1>.FBK".LFBK
INPUTMC | 4 | 3 | 0 | 3 | 14 | 3 | 1 | 3 | 16
INPUTP | 4 | 46 | 43 | 36 | 47
EXPORTS | 1 | 3 | 16
EQ | 10 | 
       EXP0_.EXP  =  din * "d<6>" * /"q<1>.FBK".LFBK * 
	"q<0>.FBK".LFBK * /"q<2>.FBK".LFBK * /"q<3>.FBK".LFBK
	+ din * "d<5>" * "q<1>.FBK".LFBK * 
	/"q<0>.FBK".LFBK * /"q<2>.FBK".LFBK * /"q<3>.FBK".LFBK
	+ /din * /"d<6>" * /"q<1>.FBK".LFBK * 
	"q<0>.FBK".LFBK * /"q<2>.FBK".LFBK * /"q<3>.FBK".LFBK
	+ /din * /"d<5>" * "q<1>.FBK".LFBK * 
	/"q<0>.FBK".LFBK * /"q<2>.FBK".LFBK * /"q<3>.FBK".LFBK
	+ /din * /"d<2>" * /"q<1>.FBK".LFBK * 
	"q<0>.FBK".LFBK * "q<2>.FBK".LFBK * /"q<3>.FBK".LFBK

MACROCELL | 3 | 17 | EXP1_
ATTRIBUTES | 2048 | 0
OUTPUTMC | 1 | 3 | 0
INPUTS | 8 | q<0>.FBK".LFBK  | q<2>.FBK".LFBK  | q<3>.FBK".LFBK  | din  | d<5>  | d<3>  | d<7>  | q<1>.FBK".LFBK
INPUTMC | 4 | 3 | 0 | 3 | 14 | 3 | 1 | 3 | 16
INPUTP | 4 | 46 | 43 | 37 | 44
EXPORTS | 1 | 3 | 0
EQ | 10 | 
       EXP1_.EXP  =  din * "d<7>" * /"q<1>.FBK".LFBK * 
	/"q<0>.FBK".LFBK * /"q<2>.FBK".LFBK * /"q<3>.FBK".LFBK
	+ din * "d<5>" * "q<1>.FBK".LFBK * 
	/"q<0>.FBK".LFBK * /"q<2>.FBK".LFBK * /"q<3>.FBK".LFBK
	+ /din * /"d<7>" * /"q<1>.FBK".LFBK * 
	/"q<0>.FBK".LFBK * /"q<2>.FBK".LFBK * /"q<3>.FBK".LFBK
	+ /din * /"d<3>" * /"q<1>.FBK".LFBK * 
	/"q<0>.FBK".LFBK * "q<2>.FBK".LFBK * /"q<3>.FBK".LFBK
	+ /din * /"d<5>" * "q<1>.FBK".LFBK * 
	/"q<0>.FBK".LFBK * /"q<2>.FBK".LFBK * /"q<3>.FBK".LFBK

PIN | clk | 64 | 0 | N/A | 49 | 4 | 3 | 16 | 3 | 0 | 3 | 14 | 3 | 1
PIN | clr | 64 | 0 | N/A | 48 | 4 | 3 | 16 | 3 | 0 | 3 | 14 | 3 | 1
PIN | din | 64 | 0 | N/A | 46 | 7 | 3 | 16 | 3 | 0 | 3 | 14 | 3 | 1 | 3 | 13 | 3 | 15 | 3 | 17
PIN | d<1> | 64 | 0 | N/A | 35 | 3 | 3 | 16 | 3 | 0 | 3 | 14
PIN | d<2> | 64 | 0 | N/A | 36 | 3 | 3 | 16 | 3 | 13 | 3 | 15
PIN | d<5> | 64 | 0 | N/A | 43 | 2 | 3 | 15 | 3 | 17
PIN | d<6> | 64 | 0 | N/A | 47 | 1 | 3 | 15
PIN | d<3> | 64 | 0 | N/A | 37 | 3 | 3 | 0 | 3 | 13 | 3 | 17
PIN | d<7> | 64 | 0 | N/A | 44 | 1 | 3 | 17
PIN | d<4> | 64 | 0 | N/A | 38 | 2 | 3 | 14 | 3 | 13
PIN | d<0> | 64 | 0 | N/A | 32 | 1 | 3 | 1
PIN | err<2> | 536871040 | 0 | N/A | 74
PIN | err<0> | 536871040 | 0 | N/A | 71
PIN | err<3> | 536871040 | 0 | N/A | 77
PIN | err<1> | 536871040 | 0 | N/A | 66
ex12.mfd - 源码说明

本页面展示了「[VHDL经典设计26例]--在xilinx芯片上调试通过--[01--1位全加器][02--2选1多路选择器][03--8位硬件加法器][04--7段数码显示译码器][05--8位串入并出寄存器][」中的 ex12.mfd 源码文件，采用 MFD 编程语言编写，共 202 行代码。您可以在线阅读完整代码内容，也可以返回资源详情页下载完整源码包进行本地学习和开发。
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