time_sim.edn

来自「[VHDL经典设计26例]--在xilinx芯片上调试通过--[01--1位全加」· EDN 代码 · 共 1,559 行 · 第 1/5 页

(edif ex12
  (edifVersion 2 0 0)
  (edifLevel 0)
  (keywordMap (keywordLevel 0))
  (status
    (written
      (timestamp 2008 3 18 9 12 40)
      (program "Xilinx ngd2edif" (version "E.38"))
      (comment "Command line: -w -v fndtn ex12.nga time_sim.edn ")))
  (external SIMPRIMS
    (edifLevel 0)
    (technology (numberDefinition
      (scale 1 (E 1 -12) (unit TIME))))
    (cell x_opad
      (cellType GENERIC)
        (view view_1
          (viewType NETLIST)
          (interface
            (port PAD
              (direction OUTPUT)
            )
          )
      )
    )
    (cell x_buf
      (cellType GENERIC)
        (view view_1
          (viewType NETLIST)
          (interface
            (port IN
              (direction INPUT)
            )
            (port OUT
              (direction OUTPUT)
            )
          )
      )
    )
    (cell x_zero
      (cellType GENERIC)
        (view view_1
          (viewType NETLIST)
          (interface
            (port OUT
              (direction OUTPUT)
            )
          )
      )
    )
    (cell x_or2
      (cellType GENERIC)
        (view view_1
          (viewType NETLIST)
          (interface
            (port IN0
              (direction INPUT)
            )
            (port IN1
              (direction INPUT)
            )
            (port OUT
              (direction OUTPUT)
            )
          )
      )
    )
    (cell x_and4
      (cellType GENERIC)
        (view view_1
          (viewType NETLIST)
          (interface
            (port IN0
              (direction INPUT)
            )
            (port IN1
              (direction INPUT)
            )
            (port IN2
              (direction INPUT)
            )
            (port IN3
              (direction INPUT)
            )
            (port OUT
              (direction OUTPUT)
            )
          )
      )
    )
    (cell x_xor2
      (cellType GENERIC)
        (view view_1
          (viewType NETLIST)
          (interface
            (port IN0
              (direction INPUT)
            )
            (port IN1
              (direction INPUT)
            )
            (port OUT
              (direction OUTPUT)
            )
          )
      )
    )
    (cell x_ff
      (cellType GENERIC)
        (view view_1
          (viewType NETLIST)
          (interface
            (port IN
              (direction INPUT)
            )
            (port CE
              (direction INPUT)
            )
            (port CLK
              (direction INPUT)
            )
            (port SET
              (direction INPUT)
            )
            (port RST
              (direction INPUT)
            )
            (port OUT
              (direction OUTPUT)
            )
          )
      )
    )
    (cell x_one
      (cellType GENERIC)
        (view view_1
          (viewType NETLIST)
          (interface
            (port OUT
              (direction OUTPUT)
            )
          )
      )
    )
    (cell x_and2
      (cellType GENERIC)
        (view view_1
          (viewType NETLIST)
          (interface
            (port IN0
              (direction INPUT)
            )
            (port IN1
              (direction INPUT)
            )
            (port OUT
              (direction OUTPUT)
            )
          )
      )
    )
    (cell x_and6
      (cellType GENERIC)
        (view view_1
          (viewType NETLIST)
          (interface
            (port IN0
              (direction INPUT)
            )
            (port IN1
              (direction INPUT)
            )
            (port IN2
              (direction INPUT)
            )
            (port IN3
              (direction INPUT)
            )
            (port IN4
              (direction INPUT)
            )
            (port IN5
              (direction INPUT)
            )
            (port OUT
              (direction OUTPUT)
            )
          )
      )
    )
    (cell x_or4
      (cellType GENERIC)
        (view view_1
          (viewType NETLIST)
          (interface
            (port IN0
              (direction INPUT)
            )
            (port IN1
              (direction INPUT)
            )
            (port IN2
              (direction INPUT)
            )
            (port IN3
              (direction INPUT)
            )
            (port OUT
              (direction OUTPUT)
            )
          )
      )
    )
    (cell x_or5
      (cellType GENERIC)
        (view view_1
          (viewType NETLIST)
          (interface
            (port IN0
              (direction INPUT)
            )
            (port IN1
              (direction INPUT)
            )
            (port IN2
              (direction INPUT)
            )
            (port IN3
              (direction INPUT)
            )
            (port IN4
              (direction INPUT)
            )
            (port OUT
              (direction OUTPUT)
            )
          )
      )
    )
    (cell x_ipad
      (cellType GENERIC)
        (view view_1
          (viewType NETLIST)
          (interface
            (port PAD
              (direction INPUT)
            )
          )
      )
    )
    (cell x_inv
      (cellType GENERIC)
        (view view_1
          (viewType NETLIST)
          (interface
            (port IN
              (direction INPUT)
            )
            (port OUT
              (direction OUTPUT)
            )
          )
      )
    )
  )

  (library ex12_lib
    (edifLevel 0)
    (technology (numberDefinition
      (scale 1 (E 1 -12) (unit TIME))))
    (cell ex12
      (cellType GENERIC)
        (view view_1
          (viewType NETLIST)
          (interface
            (port clk
              (direction INPUT)
              (designator "36")
            )
            (port clr
              (direction INPUT)
              (designator "35")
            )
            (port din
              (direction INPUT)
              (designator "33")
            )
            (port (rename d_1__ "d<1>")
              (direction INPUT)
              (designator "23")
            )
            (port (rename d_2__ "d<2>")
              (direction INPUT)
              (designator "24")
            )
            (port (rename d_5__ "d<5>")
              (direction INPUT)
              (designator "31")
            )
            (port (rename d_6__ "d<6>")
              (direction INPUT)
              (designator "34")
            )
            (port (rename err_3__ "err<3>")
              (direction OUTPUT)
              (designator "61")
            )
            (port (rename d_3__ "d<3>")
              (direction INPUT)
              (designator "25")
            )
            (port (rename d_7__ "d<7>")
              (direction INPUT)