ex12.tim

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                           Performance Summary Report
                           --------------------------

Design:     ex12
Device:     XC9572-7-PC84
Speed File: Version 3.0
Program:    Timing Report Generator:  version E.38
Date:       Tue Mar 18 09:12:38 2008

Performance Summary: 

Clock net 'clk' path delays:

Clock Pad to Output Pad (tCO)             :         15.0ns (2 macrocell levels)
Clock Pad 'clk' to Output Pad 'err<2>'                            (Pterm Clock)

Clock to Setup (tCYC)                     :          9.0ns (1 macrocell levels)
Clock to Q, net 'q<1>.Q' to DFF Setup(D) at 'q<1>.D'              (Pterm Clock)

Setup to Clock at the Pad (tSU)           :          1.5ns (0 macrocell levels)
Data signal 'din' to DFF D input Pin at 'q<1>.D'
Clock pad 'clk'                                                   (Pterm Clock)

                          Minimum Clock Period: 10.0ns
                     Maximum Internal Clock Speed: 100.0Mhz
                         (Limited by Clock Pulse Width)

--------------------------------------------------------------------------------
                      Clock Pad to Output Pad (tCO) (nsec)

\ From      c
 \          l
  \         k
   \         
    \        
     \       
      \      
  To   \------

err<2>   15.0

--------------------------------------------------------------------------------
                       Setup to Clock at Pad (tSU) (nsec)

\ From      c
 \          l
  \         k
   \         
    \        
     \       
      \      
  To   \------

d<0>      0.5
d<1>      0.5
d<2>      1.5
d<3>      1.5
d<4>      1.5
d<5>      1.5
d<6>      1.5
d<7>      1.5
din       1.5

--------------------------------------------------------------------------------
                          Clock to Setup (tCYC) (nsec)
                                  (Clock: clk)

\ From      q     q     q     q
 \          <     <     <     <
  \         0     1     2     3
   \        >     >     >     >
    \       .     .     .     .
     \      Q     Q     Q     Q
      \                        
  To   \------------------------

q<0>.D    9.0   9.0   9.0   9.0
q<1>.D    9.0   9.0   9.0   9.0
q<2>.D    9.0   9.0   9.0   9.0
q<3>.D    8.0   8.0   8.0   8.0

Path Type Definition: 

Pad to Pad (tPD) -                        Reports pad to pad paths that start 
                                          at input pads and end at output pads. 
                                          Paths are not traced through 
                                          registers. 

Clock Pad to Output Pad (tCO) -           Reports paths that start at input 
                                          pads trace through clock inputs of 
                                          registers and end at output pads. 
                                          Paths are not traced through PRE/CLR 
                                          inputs of registers. 

Setup to Clock at Pad (tSU) -             Reports external setup time of data 
                                          to clock at pad. Data path starts at 
                                          an input pad and end at register D/T 
                                          input. Clock path starts at input pad 
                                          and ends at the register clock input. 
                                          Paths are not traced through 
                                          registers. 

Clock to Setup (tCYC) -                   Register to register cycle time. 
                                          Include source register tCO and 
                                          destination register tSU.