ex12.rpt
来自「[VHDL经典设计26例]--在xilinx芯片上调试通过--[01--1位全加」· RPT 代码 · 共 416 行 · 第 1/2 页
RPT
416 行
(unused) 0 0 0 5 FB4_8 48 I/O
(unused) 0 0 0 5 FB4_9 50 I/O
(unused) 0 0 0 5 FB4_10 57 I/O
(unused) 0 0 0 5 FB4_11 53 I/O
err<2> 1 0 0 4 FB4_12 STD 58 I/O O
err<3> 0 0 \/1 4 FB4_13 STD 61 I/O O
err<0> 1 1<- \/5 0 FB4_14 STD 56 I/O O
q<2> 10 5<- 0 0 FB4_15 STD 65 I/O (b)
(unused) 0 0 \/5 0 FB4_16 62 I/O (b)
q<1> 10 5<- 0 0 FB4_17 STD 66 I/O (b)
(unused) 0 0 \/5 0 FB4_18 (b) (b)
Signals Used by Logic in Function Block
1: clk 6: "d<3>" 11: din
2: clr 7: "d<4>" 12: "q<0>.FBK".LFBK
3: "d<0>" 8: "d<5>" 13: "q<1>.FBK".LFBK
4: "d<1>" 9: "d<6>" 14: "q<2>.FBK".LFBK
5: "d<2>" 10: "d<7>" 15: "q<3>.FBK".LFBK
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
q<0> XX.X.X.X.XXXXXX......................... 11 11
q<3> XXX.......XXXXX......................... 8 8
err<1> ........................................ 0 0
err<2> ...........XXXX......................... 4 4
err<3> ........................................ 0 0
err<0> ........................................ 0 0
q<2> XX.XXXX...XXXXX......................... 11 11
q<1> XX.XX..XX.XXXXX......................... 11 11
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK/FCLK - Global clock
O - Output GTS/FOE - Global 3state/output-enable
(b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
;;-----------------------------------------------------------------;;
; Implemented Equations.
/"err<2>" = /"q<1>.FBK".LFBK * /"q<0>.FBK".LFBK *
/"q<2>.FBK".LFBK * "q<3>.FBK".LFBK
"err<0>" = ;Imported pterms FB4_13
"err<3>" = Vcc
"err<1>" = Vcc
"q<0>" := din * "d<1>" * "q<1>.FBK".LFBK *
/"q<0>.FBK".LFBK * "q<2>.FBK".LFBK * /"q<3>.FBK".LFBK
+ din * "d<3>" * /"q<1>.FBK".LFBK *
/"q<0>.FBK".LFBK * "q<2>.FBK".LFBK * /"q<3>.FBK".LFBK
+ /din * /"d<1>" * "q<1>.FBK".LFBK *
/"q<0>.FBK".LFBK * "q<2>.FBK".LFBK * /"q<3>.FBK".LFBK
;Imported pterms FB4_18
+ din * "d<7>" * /"q<1>.FBK".LFBK *
/"q<0>.FBK".LFBK * /"q<2>.FBK".LFBK * /"q<3>.FBK".LFBK
+ din * "d<5>" * "q<1>.FBK".LFBK *
/"q<0>.FBK".LFBK * /"q<2>.FBK".LFBK * /"q<3>.FBK".LFBK
+ /din * /"d<7>" * /"q<1>.FBK".LFBK *
/"q<0>.FBK".LFBK * /"q<2>.FBK".LFBK * /"q<3>.FBK".LFBK
+ /din * /"d<3>" * /"q<1>.FBK".LFBK *
/"q<0>.FBK".LFBK * "q<2>.FBK".LFBK * /"q<3>.FBK".LFBK
+ /din * /"d<5>" * "q<1>.FBK".LFBK *
/"q<0>.FBK".LFBK * /"q<2>.FBK".LFBK * /"q<3>.FBK".LFBK
"q<0>".CLKF = clk
"q<0>".RSTF = clr
"q<0>".PRLD = GND
"q<1>" := din * "d<1>" * "q<1>.FBK".LFBK *
/"q<0>.FBK".LFBK * "q<2>.FBK".LFBK * /"q<3>.FBK".LFBK
+ din * "d<2>" * /"q<1>.FBK".LFBK *
"q<0>.FBK".LFBK * "q<2>.FBK".LFBK * /"q<3>.FBK".LFBK
+ /din * /"d<1>" * "q<1>.FBK".LFBK *
/"q<0>.FBK".LFBK * "q<2>.FBK".LFBK * /"q<3>.FBK".LFBK
;Imported pterms FB4_16
+ din * "d<6>" * /"q<1>.FBK".LFBK *
"q<0>.FBK".LFBK * /"q<2>.FBK".LFBK * /"q<3>.FBK".LFBK
+ din * "d<5>" * "q<1>.FBK".LFBK *
/"q<0>.FBK".LFBK * /"q<2>.FBK".LFBK * /"q<3>.FBK".LFBK
+ /din * /"d<6>" * /"q<1>.FBK".LFBK *
"q<0>.FBK".LFBK * /"q<2>.FBK".LFBK * /"q<3>.FBK".LFBK
+ /din * /"d<5>" * "q<1>.FBK".LFBK *
/"q<0>.FBK".LFBK * /"q<2>.FBK".LFBK * /"q<3>.FBK".LFBK
+ /din * /"d<2>" * /"q<1>.FBK".LFBK *
"q<0>.FBK".LFBK * "q<2>.FBK".LFBK * /"q<3>.FBK".LFBK
"q<1>".CLKF = clk
"q<1>".RSTF = clr
"q<1>".PRLD = GND
"q<2>" := din * "d<1>" * "q<1>.FBK".LFBK *
/"q<0>.FBK".LFBK * "q<2>.FBK".LFBK * /"q<3>.FBK".LFBK
+ din * "d<4>" * "q<1>.FBK".LFBK *
"q<0>.FBK".LFBK * /"q<2>.FBK".LFBK * /"q<3>.FBK".LFBK
+ /din * /"d<1>" * "q<1>.FBK".LFBK *
/"q<0>.FBK".LFBK * "q<2>.FBK".LFBK * /"q<3>.FBK".LFBK
;Imported pterms FB4_14
+ din * "d<3>" * /"q<1>.FBK".LFBK *
/"q<0>.FBK".LFBK * "q<2>.FBK".LFBK * /"q<3>.FBK".LFBK
+ din * "d<2>" * /"q<1>.FBK".LFBK *
"q<0>.FBK".LFBK * "q<2>.FBK".LFBK * /"q<3>.FBK".LFBK
+ /din * /"d<3>" * /"q<1>.FBK".LFBK *
/"q<0>.FBK".LFBK * "q<2>.FBK".LFBK * /"q<3>.FBK".LFBK
+ /din * /"d<4>" * "q<1>.FBK".LFBK *
"q<0>.FBK".LFBK * /"q<2>.FBK".LFBK * /"q<3>.FBK".LFBK
+ /din * /"d<2>" * /"q<1>.FBK".LFBK *
"q<0>.FBK".LFBK * "q<2>.FBK".LFBK * /"q<3>.FBK".LFBK
"q<2>".CLKF = clk
"q<2>".RSTF = clr
"q<2>".PRLD = GND
"q<3>" := din * "d<0>" * "q<1>.FBK".LFBK *
"q<0>.FBK".LFBK * "q<2>.FBK".LFBK * /"q<3>.FBK".LFBK
+ /din * /"d<0>" * "q<1>.FBK".LFBK *
"q<0>.FBK".LFBK * "q<2>.FBK".LFBK * /"q<3>.FBK".LFBK
"q<3>".CLKF = clk
"q<3>".RSTF = clr
"q<3>".PRLD = GND
**************************** Device Pin Out ****************************
Device : XC9572-7-PC84
T T T G T T T T T T T T T T T T T V T T T
I I I N I I I I I I I I I I I I I C I I I
E E E D E E E E E E E E E E E E E C E E E
--------------------------------------------------------------
/11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 \
TIE | 12 74 | TIE
TIE | 13 73 | VCC
TIE | 14 72 | TIE
TIE | 15 71 | TIE
GND | 16 70 | TIE
TIE | 17 69 | TIE
TIE | 18 68 | TIE
TIE | 19 67 | TIE
d<0> | 20 66 | TIE
TIE | 21 XC9572-7-PC84 65 | TIE
VCC | 22 64 | VCC
d<1> | 23 63 | TIE
d<2> | 24 62 | TIE
d<3> | 25 61 | err<3>
d<4> | 26 60 | GND
GND | 27 59 | TDO
TDI | 28 58 | err<2>
TMS | 29 57 | TIE
TCK | 30 56 | err<0>
d<5> | 31 55 | TIE
d<7> | 32 54 | TIE
\ 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 /
--------------------------------------------------------------
d d c c T V T T T G T T T T T T G T T e T
i < l l I C I I I N I I I I I I N I I r I
n 6 r k E C E E E D E E E E E E D E E r E
> <
1
>
Legend : NC = Not Connected, unbonded pin
TIE = Tie pin to GND or board trace driven to valid logic level
VCC = Dedicated Power Pin
GND = Dedicated Ground Pin
TDI = Test Data In, JTAG pin
TDO = Test Data Out, JTAG pin
TCK = Test Clock, JTAG pin
TMS = Test Mode Select, JTAG pin
PE = Port Enable pin
PROHIBITED = User reserved pin
**************************** Compiler Options ****************************
Following is a list of all global compiler options used by the fitter run.
Device(s) Specified : XC9572-7-PC84
Use Timing Constraints : ON
Use Design Location Constraints : ON
Create Programmable Ground Pins : OFF
Use Advanced Fitting : ON
Use Local Feedback : ON
Use Pin Feedback : ON
Default Power Setting : STD
Default Output Slew Rate : FAST
Guide File Used : NONE
Multi Level Logic Optimization : ON
Timing Optimization : ON
Power/Slew Optimization : OFF
High Fitting Effort : ON
Automatic Wire-ANDing : ON
Xor Synthesis : ON
D/T Synthesis : ON
Use Boolean Minimization : ON
Global Clock(GCK) Optimization : ON
Global Set/Reset(GSR) Optimization : ON
Global Output Enable(GTS) Optimization : ON
Collapsing pterm limit : 25
Collapsing input limit : 36
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