ex12.vm6

来自「[VHDL经典设计26例]--在xilinx芯片上调试通过--[01--1位全加」· VM6 代码 · 共 662 行 · 第 1/3 页

VM6
662 行
字号
123
NODE | N_err<3>.EXP | 699 | ? | 0 | 0 | EX12_COPY_0_COPY_0 | NULL | N_err<3>.EXP | N_err<3> | 4 | 0 | MC_EXPORT
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | q<1>.FBK | 703 | ? | 0 | 0 | EX12_COPY_0_COPY_0 | NULL | q<1>.Q | q<1> | 5 | 0 | MC_FBK
OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
SIGNAL | NODE | N_err<0>.D1 | 684 | ? | 0 | 4096 | N_err<0> | NULL | NULL | N_err<0>.SI | 1 | 9 | MC_SI_D1
SPPTERM | 0 | IV_ZERO
OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
SIGNAL | NODE | N_err<0>.D2 | 685 | ? | 0 | 4096 | N_err<0> | NULL | NULL | N_err<0>.SI | 2 | 9 | MC_SI_D2
SPPTERM | 1 | IV_TRUE | N_err<3>.EXP
OUTPUT_NODE_TYPE | 7 | 9 | MC_SI_EXPORT
SIGNAL | NODE | N_err<0>.EXP | 696 | ? | 0 | 0 | N_err<0> | NULL | NULL | N_err<0>.SI | 7 | 9 | MC_SI_EXPORT
SPPTERM | 6 | IV_TRUE | N_din | IV_TRUE | N_d<3> | IV_FALSE | q<1>.FBK | IV_FALSE | q<0>.FBK | IV_TRUE | q<2>.FBK | IV_FALSE | q<3>.FBK
SPPTERM | 6 | IV_TRUE | N_din | IV_TRUE | N_d<2> | IV_FALSE | q<1>.FBK | IV_TRUE | q<0>.FBK | IV_TRUE | q<2>.FBK | IV_FALSE | q<3>.FBK
SPPTERM | 6 | IV_FALSE | N_din | IV_FALSE | N_d<3> | IV_FALSE | q<1>.FBK | IV_FALSE | q<0>.FBK | IV_TRUE | q<2>.FBK | IV_FALSE | q<3>.FBK
SPPTERM | 6 | IV_FALSE | N_din | IV_FALSE | N_d<4> | IV_TRUE | q<1>.FBK | IV_TRUE | q<0>.FBK | IV_FALSE | q<2>.FBK | IV_FALSE | q<3>.FBK
SPPTERM | 6 | IV_FALSE | N_din | IV_FALSE | N_d<2> | IV_FALSE | q<1>.FBK | IV_TRUE | q<0>.FBK | IV_TRUE | q<2>.FBK | IV_FALSE | q<3>.FBK

SRFF_INSTANCE | N_err<0>.REG | N_err<0> | 0 | 1 | 1
INPUT_NODE_TYPE | 0 | 8 | SRFF_D
NODE | N_err<0>.D | 683 | ? | 0 | 0 | N_err<0> | NULL | NULL | N_err<0>.XOR | 0 | 7 | ALU_F
OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
NODE | N_err<0>.Q | 686 | ? | 0 | 0 | N_err<0> | NULL | NULL | N_err<0>.REG | 0 | 8 | SRFF_Q

MACROCELL_INSTANCE | FbkInv+Merge+OptxMapped | N_err<3> | EX12_COPY_0_COPY_0 | 2155907072 | 0 | 3
OUTPUT_NODE_TYPE | 0 | 0 | MC_Q
NODE | N_err<3>$Q | 638 | ? | 0 | 0 | EX12_COPY_0_COPY_0 | NULL | N_err<3>.Q | N_err<3> | 0 | 0 | MC_Q
OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM
NODE | N_err<3>.UIM | 709 | ? | 0 | 0 | EX12_COPY_0_COPY_0 | NULL | N_err<3>.Q | N_err<3> | 1 | 0 | MC_UIM
OUTPUT_NODE_TYPE | 4 | 0 | MC_EXPORT
NODE | N_err<3>.EXP | 699 | ? | 0 | 0 | EX12_COPY_0_COPY_0 | NULL | N_err<3>.EXP | N_err<3> | 4 | 0 | MC_EXPORT

SIGNAL_INSTANCE | N_err<3>.SI | N_err<3> | 0 | 0 | 3
OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
SIGNAL | NODE | N_err<3>.D1 | 688 | ? | 0 | 4096 | N_err<3> | NULL | NULL | N_err<3>.SI | 1 | 9 | MC_SI_D1
SPPTERM | 0 | IV_ZERO
OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
SIGNAL | NODE | N_err<3>.D2 | 689 | ? | 0 | 4096 | N_err<3> | NULL | NULL | N_err<3>.SI | 2 | 9 | MC_SI_D2
SPPTERM | 0 | IV_DC
OUTPUT_NODE_TYPE | 7 | 9 | MC_SI_EXPORT
SIGNAL | NODE | N_err<3>.EXP | 695 | ? | 0 | 0 | N_err<3> | NULL | NULL | N_err<3>.SI | 7 | 9 | MC_SI_EXPORT
SPPTERM | 0 | IV_ZERO

SRFF_INSTANCE | N_err<3>.REG | N_err<3> | 0 | 1 | 1
INPUT_NODE_TYPE | 0 | 8 | SRFF_D
NODE | N_err<3>.D | 687 | ? | 0 | 0 | N_err<3> | NULL | NULL | N_err<3>.XOR | 0 | 7 | ALU_F
OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
NODE | N_err<3>.Q | 690 | ? | 0 | 0 | N_err<3> | NULL | NULL | N_err<3>.REG | 0 | 8 | SRFF_Q

MACROCELL_INSTANCE | OptxMapped | N_err<3>$BUF0 | EX12_COPY_0_COPY_0 | 2155872256 | 0 | 2
OUTPUT_NODE_TYPE | 0 | 0 | MC_Q
NODE | N_err<3>$BUF0 | 639 | ? | 0 | 0 | EX12_COPY_0_COPY_0 | NULL | N_err<3>$BUF0.Q | N_err<3>$BUF0 | 0 | 0 | MC_Q
OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM
NODE | N_err<3>$BUF0.UIM | 710 | ? | 0 | 0 | EX12_COPY_0_COPY_0 | NULL | N_err<3>$BUF0.Q | N_err<3>$BUF0 | 1 | 0 | MC_UIM

SIGNAL_INSTANCE | N_err<3>$BUF0.SI | N_err<3>$BUF0 | 0 | 0 | 2
OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
SIGNAL | NODE | N_err<3>$BUF0.D1 | 692 | ? | 0 | 4096 | N_err<3>$BUF0 | NULL | NULL | N_err<3>$BUF0.SI | 1 | 9 | MC_SI_D1
SPPTERM | 0 | IV_ZERO
OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
SIGNAL | NODE | N_err<3>$BUF0.D2 | 693 | ? | 0 | 6144 | N_err<3>$BUF0 | NULL | NULL | N_err<3>$BUF0.SI | 2 | 9 | MC_SI_D2
SPPTERM | 0 | IV_DC

SRFF_INSTANCE | N_err<3>$BUF0.REG | N_err<3>$BUF0 | 0 | 1 | 1
INPUT_NODE_TYPE | 0 | 8 | SRFF_D
NODE | N_err<3>$BUF0.D | 691 | ? | 0 | 0 | N_err<3>$BUF0 | NULL | NULL | N_err<3>$BUF0.XOR | 0 | 7 | ALU_F
OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
NODE | N_err<3>$BUF0.Q | 694 | ? | 0 | 0 | N_err<3>$BUF0 | NULL | NULL | N_err<3>$BUF0.REG | 0 | 8 | SRFF_Q

OUTPUT_INSTANCE | 0 | err<2> | EX12_COPY_0_COPY_0 | 3 | 1 | 1
INPUT_NODE_TYPE | 0 | 6 | OI_IN
NODE | N37 | 621 | ? | 0 | 0 | EX12_COPY_0_COPY_0 | NULL | N37.Q | N37 | 0 | 0 | MC_Q
OUTPUT_NODE_TYPE | 0 | 6 | OI_OUT
NODE | err<2> | 640 | PO | 0 | 0 | EX12_COPY_0_COPY_0 | NULL | NULL | err<2> | 0 | 6 | OI_OUT

OUTPUT_INSTANCE | 0 | err<0> | EX12_COPY_0_COPY_0 | 3 | 1 | 1
INPUT_NODE_TYPE | 0 | 6 | OI_IN
NODE | N_err<0>$Q | 637 | ? | 0 | 0 | EX12_COPY_0_COPY_0 | NULL | N_err<0>.Q | N_err<0> | 0 | 0 | MC_Q
OUTPUT_NODE_TYPE | 0 | 6 | OI_OUT
NODE | err<0> | 641 | PO | 0 | 0 | EX12_COPY_0_COPY_0 | NULL | NULL | err<0> | 0 | 6 | OI_OUT

OUTPUT_INSTANCE | 0 | err<3> | EX12_COPY_0_COPY_0 | 3 | 1 | 1
INPUT_NODE_TYPE | 0 | 6 | OI_IN
NODE | N_err<3>$Q | 638 | ? | 0 | 0 | EX12_COPY_0_COPY_0 | NULL | N_err<3>.Q | N_err<3> | 0 | 0 | MC_Q
OUTPUT_NODE_TYPE | 0 | 6 | OI_OUT
NODE | err<3> | 642 | PO | 0 | 0 | EX12_COPY_0_COPY_0 | NULL | NULL | err<3> | 0 | 6 | OI_OUT

OUTPUT_INSTANCE | 0 | err<1> | EX12_COPY_0_COPY_0 | 3 | 1 | 1
INPUT_NODE_TYPE | 0 | 6 | OI_IN
NODE | N_err<3>$BUF0 | 639 | ? | 0 | 0 | EX12_COPY_0_COPY_0 | NULL | N_err<3>$BUF0.Q | N_err<3>$BUF0 | 0 | 0 | MC_Q
OUTPUT_NODE_TYPE | 0 | 6 | OI_OUT
NODE | err<1> | 643 | PO | 0 | 0 | EX12_COPY_0_COPY_0 | NULL | NULL | err<1> | 0 | 6 | OI_OUT

MACROCELL_INSTANCE | NULL | EXP0_ | EX12_COPY_0_COPY_0 | 2147483648 | 8 | 1
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | q<0>.FBK | 704 | ? | 0 | 0 | EX12_COPY_0_COPY_0 | NULL | q<0>.Q | q<0> | 5 | 0 | MC_FBK
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | q<2>.FBK | 705 | ? | 0 | 0 | EX12_COPY_0_COPY_0 | NULL | q<2>.Q | q<2> | 5 | 0 | MC_FBK
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | q<3>.FBK | 706 | ? | 0 | 0 | EX12_COPY_0_COPY_0 | NULL | q<3>.Q | q<3> | 5 | 0 | MC_FBK
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | N_din | 628 | ? | 0 | 0 | EX12_COPY_0_COPY_0 | NULL | NULL | N_din | 0 | 5 | II_IMUX
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | N_d<5> | 633 | ? | 0 | 0 | EX12_COPY_0_COPY_0 | NULL | NULL | N_d<5> | 0 | 5 | II_IMUX
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | N_d<2> | 635 | ? | 0 | 0 | EX12_COPY_0_COPY_0 | NULL | NULL | N_d<2> | 0 | 5 | II_IMUX
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | N_d<6> | 630 | ? | 0 | 0 | EX12_COPY_0_COPY_0 | NULL | NULL | N_d<6> | 0 | 5 | II_IMUX
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | q<1>.FBK | 703 | ? | 0 | 0 | EX12_COPY_0_COPY_0 | NULL | q<1>.Q | q<1> | 5 | 0 | MC_FBK
OUTPUT_NODE_TYPE | 4 | 0 | MC_EXPORT
NODE | EXP0_.EXP | 701 | ? | 0 | 0 | EX12_COPY_0_COPY_0 | NULL | EXP0_.EXP | EXP0_ | 4 | 0 | MC_EXPORT

SIGNAL_INSTANCE | EXP0_.SI | EXP0_ | 0 | 8 | 1
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | q<0>.FBK | 704 | ? | 0 | 0 | EX12_COPY_0_COPY_0 | NULL | q<0>.Q | q<0> | 5 | 0 | MC_FBK
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | q<2>.FBK | 705 | ? | 0 | 0 | EX12_COPY_0_COPY_0 | NULL | q<2>.Q | q<2> | 5 | 0 | MC_FBK
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | q<3>.FBK | 706 | ? | 0 | 0 | EX12_COPY_0_COPY_0 | NULL | q<3>.Q | q<3> | 5 | 0 | MC_FBK
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | N_din | 628 | ? | 0 | 0 | EX12_COPY_0_COPY_0 | NULL | NULL | N_din | 0 | 5 | II_IMUX
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | N_d<5> | 633 | ? | 0 | 0 | EX12_COPY_0_COPY_0 | NULL | NULL | N_d<5> | 0 | 5 | II_IMUX
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | N_d<2> | 635 | ? | 0 | 0 | EX12_COPY_0_COPY_0 | NULL | NULL | N_d<2> | 0 | 5 | II_IMUX
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | N_d<6> | 630 | ? | 0 | 0 | EX12_COPY_0_COPY_0 | NULL | NULL | N_d<6> | 0 | 5 | II_IMUX
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | q<1>.FBK | 703 | ? | 0 | 0 | EX12_COPY_0_COPY_0 | NULL | q<1>.Q | q<1> | 5 | 0 | MC_FBK
OUTPUT_NODE_TYPE | 7 | 9 | MC_SI_EXPORT
SIGNAL | NODE | EXP0_.EXP | 697 | ? | 0 | 0 | EXP0_ | NULL | NULL | EXP0_.SI | 7 | 9 | MC_SI_EXPORT
SPPTERM | 6 | IV_TRUE | N_din | IV_TRUE | N_d<6> | IV_FALSE | q<1>.FBK | IV_TRUE | q<0>.FBK | IV_FALSE | q<2>.FBK | IV_FALSE | q<3>.FBK
SPPTERM | 6 | IV_TRUE | N_din | IV_TRUE | N_d<5> | IV_TRUE | q<1>.FBK | IV_FALSE | q<0>.FBK | IV_FALSE | q<2>.FBK | IV_FALSE | q<3>.FBK
SPPTERM | 6 | IV_FALSE | N_din | IV_FALSE | N_d<6> | IV_FALSE | q<1>.FBK | IV_TRUE | q<0>.FBK | IV_FALSE | q<2>.FBK | IV_FALSE | q<3>.FBK
SPPTERM | 6 | IV_FALSE | N_din | IV_FALSE | N_d<5> | IV_TRUE | q<1>.FBK | IV_FALSE | q<0>.FBK | IV_FALSE | q<2>.FBK | IV_FALSE | q<3>.FBK
SPPTERM | 6 | IV_FALSE | N_din | IV_FALSE | N_d<2> | IV_FALSE | q<1>.FBK | IV_TRUE | q<0>.FBK | IV_TRUE | q<2>.FBK | IV_FALSE | q<3>.FBK

MACROCELL_INSTANCE | NULL | EXP1_ | EX12_COPY_0_COPY_0 | 2147483648 | 8 | 1
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | q<0>.FBK | 704 | ? | 0 | 0 | EX12_COPY_0_COPY_0 | NULL | q<0>.Q | q<0> | 5 | 0 | MC_FBK
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | q<2>.FBK | 705 | ? | 0 | 0 | EX12_COPY_0_COPY_0 | NULL | q<2>.Q | q<2> | 5 | 0 | MC_FBK
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | q<3>.FBK | 706 | ? | 0 | 0 | EX12_COPY_0_COPY_0 | NULL | q<3>.Q | q<3> | 5 | 0 | MC_FBK
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | N_din | 628 | ? | 0 | 0 | EX12_COPY_0_COPY_0 | NULL | NULL | N_din | 0 | 5 | II_IMUX
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | N_d<5> | 633 | ? | 0 | 0 | EX12_COPY_0_COPY_0 | NULL | NULL | N_d<5> | 0 | 5 | II_IMUX
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | N_d<3> | 632 | ? | 0 | 0 | EX12_COPY_0_COPY_0 | NULL | NULL | N_d<3> | 0 | 5 | II_IMUX
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | N_d<7> | 629 | ? | 0 | 0 | EX12_COPY_0_COPY_0 | NULL | NULL | N_d<7> | 0 | 5 | II_IMUX
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | q<1>.FBK | 703 | ? | 0 | 0 | EX12_COPY_0_COPY_0 | NULL | q<1>.Q | q<1> | 5 | 0 | MC_FBK
OUTPUT_NODE_TYPE | 4 | 0 | MC_EXPORT
NODE | EXP1_.EXP | 702 | ? | 0 | 0 | EX12_COPY_0_COPY_0 | NULL | EXP1_.EXP | EXP1_ | 4 | 0 | MC_EXPORT

SIGNAL_INSTANCE | EXP1_.SI | EXP1_ | 0 | 8 | 1
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | q<0>.FBK | 704 | ? | 0 | 0 | EX12_COPY_0_COPY_0 | NULL | q<0>.Q | q<0> | 5 | 0 | MC_FBK
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | q<2>.FBK | 705 | ? | 0 | 0 | EX12_COPY_0_COPY_0 | NULL | q<2>.Q | q<2> | 5 | 0 | MC_FBK
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | q<3>.FBK | 706 | ? | 0 | 0 | EX12_COPY_0_COPY_0 | NULL | q<3>.Q | q<3> | 5 | 0 | MC_FBK
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | N_din | 628 | ? | 0 | 0 | EX12_COPY_0_COPY_0 | NULL | NULL | N_din | 0 | 5 | II_IMUX
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | N_d<5> | 633 | ? | 0 | 0 | EX12_COPY_0_COPY_0 | NULL | NULL | N_d<5> | 0 | 5 | II_IMUX
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | N_d<3> | 632 | ? | 0 | 0 | EX12_COPY_0_COPY_0 | NULL | NULL | N_d<3> | 0 | 5 | II_IMUX
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | N_d<7> | 629 | ? | 0 | 0 | EX12_COPY_0_COPY_0 | NULL | NULL | N_d<7> | 0 | 5 | II_IMUX
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | q<1>.FBK | 703 | ? | 0 | 0 | EX12_COPY_0_COPY_0 | NULL | q<1>.Q | q<1> | 5 | 0 | MC_FBK
OUTPUT_NODE_TYPE | 7 | 9 | MC_SI_EXPORT
SIGNAL | NODE | EXP1_.EXP | 698 | ? | 0 | 0 | EXP1_ | NULL | NULL | EXP1_.SI | 7 | 9 | MC_SI_EXPORT
SPPTERM | 6 | IV_TRUE | N_din | IV_TRUE | N_d<7> | IV_FALSE | q<1>.FBK | IV_FALSE | q<0>.FBK | IV_FALSE | q<2>.FBK | IV_FALSE | q<3>.FBK
SPPTERM | 6 | IV_TRUE | N_din | IV_TRUE | N_d<5> | IV_TRUE | q<1>.FBK | IV_FALSE | q<0>.FBK | IV_FALSE | q<2>.FBK | IV_FALSE | q<3>.FBK
SPPTERM | 6 | IV_FALSE | N_din | IV_FALSE | N_d<7> | IV_FALSE | q<1>.FBK | IV_FALSE | q<0>.FBK | IV_FALSE | q<2>.FBK | IV_FALSE | q<3>.FBK
SPPTERM | 6 | IV_FALSE | N_din | IV_FALSE | N_d<3> | IV_FALSE | q<1>.FBK | IV_FALSE | q<0>.FBK | IV_TRUE | q<2>.FBK | IV_FALSE | q<3>.FBK
SPPTERM | 6 | IV_FALSE | N_din | IV_FALSE | N_d<5> | IV_TRUE | q<1>.FBK | IV_FALSE | q<0>.FBK | IV_FALSE | q<2>.FBK | IV_FALSE | q<3>.FBK

FB_INSTANCE | FOOBAR1_ | EX12_COPY_0_COPY_0 | 0 | 0 | 0
FBPIN | 13 | NULL | 0 | N_d<0> | 0 | NULL | 0 | 20 | 49152
FBPIN | 16 | NULL | 0 | N_d<1> | 0 | NULL | 0 | 23 | 49152
FBPIN | 18 | NULL | 0 | N_d<2> | 0 | NULL | 0 | 24 | 49152

FB_INSTANCE | FOOBAR2_ | EX12_COPY_0_COPY_0 | 0 | 0 | 0

FB_INSTANCE | FOOBAR3_ | EX12_COPY_0_COPY_0 | 0 | 0 | 0
FBPIN | 1 | NULL | 0 | N_d<3> | 0 | NULL | 0 | 25 | 49152
FBPIN | 3 | NULL | 0 | N_d<5> | 0 | NULL | 0 | 31 | 49152
FBPIN | 4 | NULL | 0 | N_d<7> | 0 | NULL | 0 | 32 | 49152
FBPIN | 6 | NULL | 0 | N_d<6> | 0 | NULL | 0 | 34 | 49152
FBPIN | 7 | NULL | 0 | N_clr | 0 | NULL | 0 | 35 | 49152
FBPIN | 9 | NULL | 0 | N_d<4> | 0 | NULL | 0 | 26 | 49152
FBPIN | 11 | NULL | 0 | N_din | 0 | NULL | 0 | 33 | 49152
FBPIN | 14 | NULL | 0 | N_clk | 0 | NULL | 0 | 36 | 49152

FB_INSTANCE | FOOBAR4_ | EX12_COPY_0_COPY_0 | 0 | 0 | 0
FBPIN | 1 | q<0> | 1 | NULL | 0 | NULL | 0 | 46 | 49152
FBPIN | 2 | q<3> | 1 | NULL | 0 | NULL | 0 | 44 | 49152
FBPIN | 4 | N_err<3>$BUF0 | 1 | NULL | 0 | err<1> | 1 | 52 | 49152
FBPIN | 12 | N37 | 1 | NULL | 0 | err<2> | 1 | 58 | 49152
FBPIN | 13 | N_err<3> | 1 | NULL | 0 | err<3> | 1 | 61 | 49152
FBPIN | 14 | N_err<0> | 1 | NULL | 0 | err<0> | 1 | 56 | 49152
FBPIN | 15 | q<2> | 1 | NULL | 0 | NULL | 0 | 65 | 49152
FBPIN | 16 | EXP0_ | 1 | NULL | 0 | NULL | 0 | 62 | 49152
FBPIN | 17 | q<1> | 1 | NULL | 0 | NULL | 0 | 66 | 49152
FBPIN | 18 | EXP1_ | 1 | NULL | 0 | NULL | 0

FB_INSTANCE | INPUTPINS_FOOBAR5_ | EX12_COPY_0_COPY_0 | 0 | 0 | 0

FB_ORDER_OF_INPUTS | FOOBAR4_ | 0 | q<0>.FBK | NULL | 1 | q<3>.FBK | NULL | 4 | clr | 35 | 6 | d<1> | 23 | 10 | d<6> | 34
FB_ORDER_OF_INPUTS | FOOBAR4_ | 12 | d<3> | 25 | 14 | q<2>.FBK | NULL | 15 | d<4> | 26 | 16 | q<1>.FBK | NULL | 20 | d<7> | 32
FB_ORDER_OF_INPUTS | FOOBAR4_ | 24 | clk | 36 | 25 | d<2> | 24 | 33 | din | 33 | 34 | d<5> | 31 | 35 | d<0> | 20

FB_IMUX_INDEX | FOOBAR4_ | 0 | 1 | -1 | -1 | 126 | -1 | 132 | -1 | -1 | -1 | 130 | -1 | 138 | -1 | 14 | 87 | 16 | -1 | -1 | -1 | 110 | -1 | -1 | -1 | 104 | 140 | -1 | -1 | -1 | -1 | -1 | -1 | -1 | 86 | 122 | 123
123

ex12.vm6 - 源码说明

本页面展示了「[VHDL经典设计26例]--在xilinx芯片上调试通过--[01--1位全加器][02--2选1多路选择器][03--8位硬件加法器][04--7段数码显示译码器][05--8位串入并出寄存器][」中的 ex12.vm6 源码文件，采用 VM6 编程语言编写，共 662 行代码。您可以在线阅读完整代码内容，也可以返回资源详情页下载完整源码包进行本地学习和开发。

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