ex7.mod

来自「[VHDL经典设计26例]--在xilinx芯片上调试通过--[01--1位全加」· MOD 代码 · 共 33 行

MODEL
MODEL_VERSION "v1998.8";
DESIGN "ex7";

/* port names and type */
INPUT S:PIN26 = bin<0>;
INPUT S:PIN36 = sel;
INPUT S:PIN20 = ain<0>;
INPUT S:PIN31 = bin<1>;
INPUT S:PIN23 = ain<1>;
INPUT S:PIN34 = bin<2>;
INPUT S:PIN24 = ain<2>;
INPUT S:PIN32 = bin<3>;
INPUT S:PIN25 = ain<3>;
OUTPUT S:PIN56 = q<0>;
OUTPUT S:PIN52 = q<1>;
OUTPUT S:PIN58 = q<2>;
OUTPUT S:PIN61 = q<3>;

/* timing arc definitions */
bin<0>_q<0>_delay: DELAY bin<0> q<0>;
ain<0>_q<0>_delay: DELAY ain<0> q<0>;
bin<1>_q<1>_delay: DELAY bin<1> q<1>;
ain<1>_q<1>_delay: DELAY ain<1> q<1>;
bin<2>_q<2>_delay: DELAY bin<2> q<2>;
ain<2>_q<2>_delay: DELAY ain<2> q<2>;
bin<3>_q<3>_delay: DELAY bin<3> q<3>;
ain<3>_q<3>_delay: DELAY ain<3> q<3>;

/* timing check arc definitions */

ENDMODEL