time_sim.edn
来自「[VHDL经典设计26例]--在xilinx芯片上调试通过--[01--1位全加」· EDN 代码 · 共 1,694 行 · 第 1/5 页
EDN
1,694 行
(instance (rename q_3___61 "q_3_&_61") (viewRef view_1 (cellRef x_buf (libraryRef SIMPRIMS))) (portInstance OUT (property RISE (integer 2500) (unit TIME) (owner "Xilinx")) (property FALL (integer 2500) (unit TIME) (owner "Xilinx")) ) ) (instance N_q_3__BUF0_62 (viewRef view_1 (cellRef x_buf (libraryRef SIMPRIMS))) ) (instance N_q_3__BUF0_REG (viewRef view_1 (cellRef x_buf (libraryRef SIMPRIMS))) (portInstance OUT (property RISE (integer 500) (unit TIME) (owner "Xilinx")) (property FALL (integer 500) (unit TIME) (owner "Xilinx")) ) ) (instance N_q_3__BUF0_D1_63 (viewRef view_1 (cellRef x_or2 (libraryRef SIMPRIMS))) ) (instance N_q_3__BUF0_D2_PT_0_64 (viewRef view_1 (cellRef x_and2 (libraryRef SIMPRIMS))) (portInstance IN0 (property RISE (integer 2000) (unit TIME) (owner "Xilinx")) (property FALL (integer 2000) (unit TIME) (owner "Xilinx")) ) (portInstance IN1 (property RISE (integer 2000) (unit TIME) (owner "Xilinx")) (property FALL (integer 2000) (unit TIME) (owner "Xilinx")) ) ) (instance N_q_3__BUF0_D2_65 (viewRef view_1 (cellRef x_or2 (libraryRef SIMPRIMS))) ) (instance N_q_3__BUF0_XOR (viewRef view_1 (cellRef x_xor2 (libraryRef SIMPRIMS))) ) (instance (rename N_q_3___66 "N_q_3_&_66") (viewRef view_1 (cellRef x_and2 (libraryRef SIMPRIMS))) ) (instance N_q_3__WA0_BUFOE (viewRef view_1 (cellRef x_buf (libraryRef SIMPRIMS))) ) (instance N_q_3__WA0_TRST_PT_0_67 (viewRef view_1 (cellRef x_and2 (libraryRef SIMPRIMS))) (portInstance IN0 (property RISE (integer 7000) (unit TIME) (owner "Xilinx")) (property FALL (integer 7000) (unit TIME) (owner "Xilinx")) ) (portInstance IN1 (property RISE (integer 7000) (unit TIME) (owner "Xilinx")) (property FALL (integer 7000) (unit TIME) (owner "Xilinx")) ) ) (instance N_q_3__WA0_TRST_68 (viewRef view_1 (cellRef x_or2 (libraryRef SIMPRIMS))) ) (instance N_q_3__WA0_69 (viewRef view_1 (cellRef x_or2 (libraryRef SIMPRIMS))) ) (instance N_q_3__WA0_REG (viewRef view_1 (cellRef x_buf (libraryRef SIMPRIMS))) (portInstance OUT (property RISE (integer 500) (unit TIME) (owner "Xilinx")) (property FALL (integer 500) (unit TIME) (owner "Xilinx")) ) ) (instance N_q_3__WA0_D1_70 (viewRef view_1 (cellRef x_or2 (libraryRef SIMPRIMS))) ) (instance N_q_3__WA0_D2_PT_0_71 (viewRef view_1 (cellRef x_and2 (libraryRef SIMPRIMS))) (portInstance IN0 (property RISE (integer 2000) (unit TIME) (owner "Xilinx")) (property FALL (integer 2000) (unit TIME) (owner "Xilinx")) ) (portInstance IN1 (property RISE (integer 2000) (unit TIME) (owner "Xilinx")) (property FALL (integer 2000) (unit TIME) (owner "Xilinx")) ) ) (instance N_q_3__WA0_D2_72 (viewRef view_1 (cellRef x_or2 (libraryRef SIMPRIMS))) ) (instance N_q_3__WA0_XOR (viewRef view_1 (cellRef x_xor2 (libraryRef SIMPRIMS))) ) (instance bin_3__PAD (viewRef view_1 (cellRef x_ipad (libraryRef SIMPRIMS))) ) (instance (rename N_bin_3___73 "N_bin_3_&_73") (viewRef view_1 (cellRef x_buf (libraryRef SIMPRIMS))) (portInstance OUT (property RISE (integer 2500) (unit TIME) (owner "Xilinx")) (property FALL (integer 2500) (unit TIME) (owner "Xilinx")) ) ) (instance N_q_3__WA1_BUFOE (viewRef view_1 (cellRef x_buf (libraryRef SIMPRIMS))) ) (instance N_q_3__WA1_TRST_PT_0_74 (viewRef view_1 (cellRef x_and2 (libraryRef SIMPRIMS))) (portInstance IN0 (property RISE (integer 7000) (unit TIME) (owner "Xilinx")) (property FALL (integer 7000) (unit TIME) (owner "Xilinx")) ) (portInstance IN1 (property RISE (integer 7000) (unit TIME) (owner "Xilinx")) (property FALL (integer 7000) (unit TIME) (owner "Xilinx")) ) ) (instance N_q_3__WA1_TRST_75 (viewRef view_1 (cellRef x_or2 (libraryRef SIMPRIMS))) ) (instance N_q_3__WA1_76 (viewRef view_1 (cellRef x_or2 (libraryRef SIMPRIMS))) ) (instance N_q_3__WA1_REG (viewRef view_1 (cellRef x_buf (libraryRef SIMPRIMS))) (portInstance OUT (property RISE (integer 500) (unit TIME) (owner "Xilinx")) (property FALL (integer 500) (unit TIME) (owner "Xilinx")) ) ) (instance N_q_3__WA1_D1_77 (viewRef view_1 (cellRef x_or2 (libraryRef SIMPRIMS))) ) (instance N_q_3__WA1_D2_PT_0_78 (viewRef view_1 (cellRef x_and2 (libraryRef SIMPRIMS))) (portInstance IN0 (property RISE (integer 2000) (unit TIME) (owner "Xilinx")) (property FALL (integer 2000) (unit TIME) (owner "Xilinx")) ) (portInstance IN1 (property RISE (integer 2000) (unit TIME) (owner "Xilinx")) (property FALL (integer 2000) (unit TIME) (owner "Xilinx")) ) ) (instance N_q_3__WA1_D2_79 (viewRef view_1 (cellRef x_or2 (libraryRef SIMPRIMS))) ) (instance N_q_3__WA1_XOR (viewRef view_1 (cellRef x_xor2 (libraryRef SIMPRIMS))) ) (instance ain_3__PAD (viewRef view_1 (cellRef x_ipad (libraryRef SIMPRIMS))) ) (instance (rename N_ain_3___80 "N_ain_3_&_80") (viewRef view_1 (cellRef x_buf (libraryRef SIMPRIMS))) (portInstance OUT (property RISE (integer 2500) (unit TIME) (owner "Xilinx")) (property FALL (integer 2500) (unit TIME) (owner "Xilinx")) ) ) (instance NlwInverterBlock_N_q_0__WA0_IN1 (viewRef view_1 (cellRef x_inv (libraryRef SIMPRIMS))) ) (instance NlwInverterBlock_N_q_0__WA1_TRST_PT_0_IN0 (viewRef view_1 (cellRef x_inv (libraryRef SIMPRIMS))) ) (instance NlwInverterBlock_N_q_0__WA1_TRST_PT_0_IN1 (viewRef view_1 (cellRef x_inv (libraryRef SIMPRIMS))) ) (instance NlwInverterBlock_N_q_0__WA1_IN1 (viewRef view_1 (cellRef x_inv (libraryRef SIMPRIMS))) ) (instance NlwInverterBlock_N_q_1__WA0_IN1 (viewRef view_1 (cellRef x_inv (libraryRef SIMPRIMS))) ) (instance NlwInverterBlock_N_q_1__WA1_TRST_PT_0_IN0 (viewRef view_1 (cellRef x_inv (libraryRef SIMPRIMS))) ) (instance NlwInverterBlock_N_q_1__WA1_TRST_PT_0_IN1 (viewRef view_1 (cellRef x_inv (libraryRef SIMPRIMS))) ) (instance NlwInverterBlock_N_q_1__WA1_IN1 (viewRef view_1 (cellRef x_inv (libraryRef SIMPRIMS))) ) (instance NlwInverterBlock_N_q_2__WA0_IN1 (viewRef view_1 (cellRef x_inv (libraryRef SIMPRIMS))) ) (instance NlwInverterBlock_N_q_2__WA1_TRST_PT_0_IN0 (viewRef view_1 (cellRef x_inv (libraryRef SIMPRIMS))) ) (instance NlwInverterBlock_N_q_2__WA1_TRST_PT_0_IN1 (viewRef view_1 (cellRef x_inv (libraryRef SIMPRIMS))) ) (instance NlwInverterBlock_N_q_2__WA1_IN1 (viewRef view_1 (cellRef x_inv (libraryRef SIMPRIMS))) ) (instance NlwInverterBlock_N_q_3__WA0_IN1 (viewRef view_1 (cellRef x_inv (libraryRef SIMPRIMS))) ) (instance NlwInverterBlock_N_q_3__WA1_TRST_PT_0_IN0 (viewRef view_1 (cellRef x_inv (libraryRef SIMPRIMS))) ) (instance NlwInverterBlock_N_q_3__WA1_TRST_PT_0_IN1 (viewRef view_1 (cellRef x_inv (libraryRef SIMPRIMS))) ) (instance NlwInverterBlock_N_q_3__WA1_IN1 (viewRef view_1 (cellRef x_inv (libraryRef SIMPRIMS))) ) (net (rename bin_0__ "bin<0>") (joined (portRef bin_0__) (portRef PAD (instanceRef bin_0__PAD)) (portRef IN (instanceRef N_bin_0___12)) ) ) (net sel (joined (portRef sel) (portRef PAD (instanceRef sel_PAD)) (portRef IN (instanceRef N_sel_13)) ) ) (net (rename ain_0__ "ain<0>") (joined (portRef ain_0__) (portRef PAD (instanceRef ain_0__PAD)) (portRef IN (instanceRef N_ain_0___20)) ) ) (net (rename bin_1__ "bin<1>") (joined (portRef bin_1__) (portRef PAD (instanceRef bin_1__PAD)) (portRef IN (instanceRef N_bin_1___33)) ) ) (net (rename ain_1__ "ain<1>") (joined (portRef ain_1__) (portRef PAD (instanceRef ain_1__PAD)) (portRef IN (instanceRef N_ain_1___40)) ) ) (net (rename bin_2__ "bin<2>") (joined (portRef bin_2__) (portRef PAD (instanceRef bin_2__PAD)) (portRef IN (instanceRef N_bin_2___53)) ) ) (net (rename ain_2__ "ain<2>") (joined (portRef ain_2__) (portRef PAD (instanceRef ain_2__PAD)) (portRef IN (instanceRef N_ain_2___60)) ) ) (net (rename bin_3__ "bin<3>") (joined (portRef bin_3__) (portRef PAD (instanceRef bin_3__PAD)) (portRef IN (instanceRef N_bin_3___73)) ) ) (net (rename ain_3__ "ain<3>") (joined (portRef ain_3__) (portRef PAD (instanceRef ain_3__PAD)) (portRef IN (instanceRef N_ain_3___80)) ) ) (net (rename q_0__ "q<0>") (joined (portRef q_0__) (portRef PAD (instanceRef q_0__PAD)) (portRef OUT (instanceRef q_0___0)) ) ) (net (rename q_1__ "q<1>") (joined (portRef q_1__) (portRef PAD (instanceRef q_1__PAD)) (portRef OUT (instanceRef q_1___21)) ) ) (net (rename q_2__ "q<2>") (joined (portRef q_2__) (portRef PAD (instanceRef q_2__PAD)) (portRef OUT (instanceRef q_2___41)) ) ) (net (rename q_3__ "q<3>") (joined (portRef q_3__) (portRef PAD (instanceRef q_3__PAD)) (portRef OUT (instanceRef q_3___61)) ) ) (net N_q_0__BUF0 (joined (portRef IN (instanceRef q_0___0)) (portRef OUT (instanceRef N_q_0__BUF0_1)) ) ) (net N_q_0__BUF0_Q (joined (portRef IN (instanceRef N_q_0__BUF0_1)) (portRef OUT (instanceRef N_q_0__BUF0_REG)) ) ) (net N_q_0__BUF0_D (joined (portRef IN (instanceRef N_q_0__BUF0_REG)) (portRef OUT (instanceRef N_q_0__BUF0_XOR)) ) ) (net N_q_0__BUF0_D1 (joined (portRef OUT (instanceRef N_q_0__BUF0_D1_2)) (portRef IN0 (instanceRef N_q_0__BUF0_XOR)) ) ) (net (rename N_q_0__ "N_q<0>") (joined (portRef IN0 (instanceRef N_q_0__BUF0_D2_PT_0_3)) (portRef IN1 (instanceRef N_q_0__BUF0_D2_PT_0_3)) (portRef OUT (instanceRef N_q_0___5)) ) ) (net N_q_0__BUF0_D2_PT_0 (joined (portRef OUT (instanceRef N_q_0__BUF0_D2_PT_0_3)) (portRef IN0 (instanceRef N_q_0__BUF0_D2_4)) (portRef IN1 (instanceRef N_q_0__BUF0_D2_4)) ) ) (net N_q_0__BUF0_D2 (joined (portRef OUT (instanceRef N_q_0__BUF0_D2_4)) (portRef IN1 (instanceRef N_q_0__BUF0_XOR)) ) ) (net N_q_0__WA0 (joined
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