time_sim.edn
来自「[VHDL经典设计26例]--在xilinx芯片上调试通过--[01--1位全加」· EDN 代码 · 共 1,694 行 · 第 1/5 页
EDN
1,694 行
(edif ex7 (edifVersion 2 0 0) (edifLevel 0) (keywordMap (keywordLevel 0)) (status (written (timestamp 2008 3 12 9 0 51) (program "Xilinx ngd2edif" (version "E.38")) (comment "Command line: -w -v fndtn ex7.nga time_sim.edn "))) (external SIMPRIMS (edifLevel 0) (technology (numberDefinition (scale 1 (E 1 -12) (unit TIME)))) (cell x_opad (cellType GENERIC) (view view_1 (viewType NETLIST) (interface (port PAD (direction OUTPUT) ) ) ) ) (cell x_buf (cellType GENERIC) (view view_1 (viewType NETLIST) (interface (port IN (direction INPUT) ) (port OUT (direction OUTPUT) ) ) ) ) (cell x_zero (cellType GENERIC) (view view_1 (viewType NETLIST) (interface (port OUT (direction OUTPUT) ) ) ) ) (cell x_or2 (cellType GENERIC) (view view_1 (viewType NETLIST) (interface (port IN0 (direction INPUT) ) (port IN1 (direction INPUT) ) (port OUT (direction OUTPUT) ) ) ) ) (cell x_and2 (cellType GENERIC) (view view_1 (viewType NETLIST) (interface (port IN0 (direction INPUT) ) (port IN1 (direction INPUT) ) (port OUT (direction OUTPUT) ) ) ) ) (cell x_xor2 (cellType GENERIC) (view view_1 (viewType NETLIST) (interface (port IN0 (direction INPUT) ) (port IN1 (direction INPUT) ) (port OUT (direction OUTPUT) ) ) ) ) (cell x_ipad (cellType GENERIC) (view view_1 (viewType NETLIST) (interface (port PAD (direction INPUT) ) ) ) ) (cell x_inv (cellType GENERIC) (view view_1 (viewType NETLIST) (interface (port IN (direction INPUT) ) (port OUT (direction OUTPUT) ) ) ) ) ) (library ex7_lib (edifLevel 0) (technology (numberDefinition (scale 1 (E 1 -12) (unit TIME)))) (cell ex7 (cellType GENERIC) (view view_1 (viewType NETLIST) (interface (port (rename bin_0__ "bin<0>") (direction INPUT) (designator "26") ) (port sel (direction INPUT) (designator "36") ) (port (rename ain_0__ "ain<0>") (direction INPUT) (designator "20") ) (port (rename bin_1__ "bin<1>") (direction INPUT) (designator "31") ) (port (rename ain_1__ "ain<1>") (direction INPUT) (designator "23") ) (port (rename bin_2__ "bin<2>") (direction INPUT) (designator "34") ) (port (rename ain_2__ "ain<2>") (direction INPUT) (designator "24") ) (port (rename bin_3__ "bin<3>") (direction INPUT) (designator "32") ) (port (rename ain_3__ "ain<3>") (direction INPUT) (designator "25") ) (port (rename q_0__ "q<0>") (direction OUTPUT) (designator "56") ) (port (rename q_1__ "q<1>") (direction OUTPUT) (designator "52") ) (port (rename q_2__ "q<2>") (direction OUTPUT) (designator "58") ) (port (rename q_3__ "q<3>") (direction OUTPUT) (designator "61") ) (designator "XC9572-7-PC84") ) (contents (instance q_0__PAD (viewRef view_1 (cellRef x_opad (libraryRef SIMPRIMS))) ) (instance (rename q_0___0 "q_0_&_0") (viewRef view_1 (cellRef x_buf (libraryRef SIMPRIMS))) (portInstance OUT (property RISE (integer 2500) (unit TIME) (owner "Xilinx")) (property FALL (integer 2500) (unit TIME) (owner "Xilinx")) ) ) (instance N_q_0__BUF0_1 (viewRef view_1 (cellRef x_buf (libraryRef SIMPRIMS))) ) (instance N_q_0__BUF0_REG (viewRef view_1 (cellRef x_buf (libraryRef SIMPRIMS))) (portInstance OUT (property RISE (integer 500) (unit TIME) (owner "Xilinx")) (property FALL (integer 500) (unit TIME) (owner "Xilinx")) ) ) (instance GND_ZERO (viewRef view_1 (cellRef x_zero (libraryRef SIMPRIMS))) ) (instance N_q_0__BUF0_D1_2 (viewRef view_1 (cellRef x_or2 (libraryRef SIMPRIMS))) ) (instance N_q_0__BUF0_D2_PT_0_3 (viewRef view_1 (cellRef x_and2 (libraryRef SIMPRIMS))) (portInstance IN0 (property RISE (integer 2000) (unit TIME) (owner "Xilinx")) (property FALL (integer 2000) (unit TIME) (owner "Xilinx")) ) (portInstance IN1 (property RISE (integer 2000) (unit TIME) (owner "Xilinx")) (property FALL (integer 2000) (unit TIME) (owner "Xilinx")) ) ) (instance N_q_0__BUF0_D2_4 (viewRef view_1 (cellRef x_or2 (libraryRef SIMPRIMS))) ) (instance N_q_0__BUF0_XOR (viewRef view_1 (cellRef x_xor2 (libraryRef SIMPRIMS))) ) (instance (rename N_q_0___5 "N_q_0_&_5") (viewRef view_1 (cellRef x_and2 (libraryRef SIMPRIMS))) ) (instance N_q_0__WA0_BUFOE (viewRef view_1 (cellRef x_buf (libraryRef SIMPRIMS))) ) (instance N_q_0__WA0_TRST_PT_0_6 (viewRef view_1 (cellRef x_and2 (libraryRef SIMPRIMS))) (portInstance IN0 (property RISE (integer 7000) (unit TIME) (owner "Xilinx")) (property FALL (integer 7000) (unit TIME) (owner "Xilinx")) ) (portInstance IN1 (property RISE (integer 7000) (unit TIME) (owner "Xilinx")) (property FALL (integer 7000) (unit TIME) (owner "Xilinx")) ) ) (instance N_q_0__WA0_TRST_7 (viewRef view_1 (cellRef x_or2 (libraryRef SIMPRIMS))) ) (instance N_q_0__WA0_8 (viewRef view_1 (cellRef x_or2 (libraryRef SIMPRIMS))) ) (instance N_q_0__WA0_REG (viewRef view_1 (cellRef x_buf (libraryRef SIMPRIMS))) (portInstance OUT (property RISE (integer 500) (unit TIME) (owner "Xilinx")) (property FALL (integer 500) (unit TIME) (owner "Xilinx")) ) ) (instance N_q_0__WA0_D1_9 (viewRef view_1 (cellRef x_or2 (libraryRef SIMPRIMS))) ) (instance N_q_0__WA0_D2_PT_0_10 (viewRef view_1 (cellRef x_and2 (libraryRef SIMPRIMS))) (portInstance IN0 (property RISE (integer 2000) (unit TIME) (owner "Xilinx")) (property FALL (integer 2000) (unit TIME) (owner "Xilinx")) ) (portInstance IN1 (property RISE (integer 2000) (unit TIME) (owner "Xilinx")) (property FALL (integer 2000) (unit TIME) (owner "Xilinx")) ) ) (instance N_q_0__WA0_D2_11 (viewRef view_1 (cellRef x_or2 (libraryRef SIMPRIMS))) ) (instance N_q_0__WA0_XOR (viewRef view_1 (cellRef x_xor2 (libraryRef SIMPRIMS))) ) (instance bin_0__PAD (viewRef view_1 (cellRef x_ipad (libraryRef SIMPRIMS))) ) (instance (rename N_bin_0___12 "N_bin_0_&_12") (viewRef view_1 (cellRef x_buf (libraryRef SIMPRIMS))) (portInstance OUT (property RISE (integer 2500) (unit TIME) (owner "Xilinx")) (property FALL (integer 2500) (unit TIME) (owner "Xilinx")) ) ) (instance sel_PAD (viewRef view_1 (cellRef x_ipad (libraryRef SIMPRIMS))) ) (instance N_sel_13 (viewRef view_1 (cellRef x_buf (libraryRef SIMPRIMS))) (portInstance OUT (property RISE (integer 2500) (unit TIME) (owner "Xilinx")) (property FALL (integer 2500) (unit TIME) (owner "Xilinx")) ) ) (instance N_q_0__WA1_BUFOE (viewRef view_1 (cellRef x_buf (libraryRef SIMPRIMS))) ) (instance N_q_0__WA1_TRST_PT_0_14 (viewRef view_1 (cellRef x_and2 (libraryRef SIMPRIMS))) (portInstance IN0 (property RISE (integer 7000) (unit TIME) (owner "Xilinx")) (property FALL (integer 7000) (unit TIME) (owner "Xilinx")) ) (portInstance IN1 (property RISE (integer 7000) (unit TIME) (owner "Xilinx")) (property FALL (integer 7000) (unit TIME) (owner "Xilinx")) ) ) (instance N_q_0__WA1_TRST_15 (viewRef view_1 (cellRef x_or2 (libraryRef SIMPRIMS))) ) (instance N_q_0__WA1_16 (viewRef view_1 (cellRef x_or2 (libraryRef SIMPRIMS))) ) (instance N_q_0__WA1_REG (viewRef view_1 (cellRef x_buf (libraryRef SIMPRIMS))) (portInstance OUT (property RISE (integer 500) (unit TIME) (owner "Xilinx")) (property FALL (integer 500) (unit TIME) (owner "Xilinx")) ) ) (instance N_q_0__WA1_D1_17 (viewRef view_1 (cellRef x_or2 (libraryRef SIMPRIMS))) ) (instance N_q_0__WA1_D2_PT_0_18 (viewRef view_1 (cellRef x_and2 (libraryRef SIMPRIMS))) (portInstance IN0 (property RISE (integer 2000) (unit TIME) (owner "Xilinx")) (property FALL (integer 2000) (unit TIME) (owner "Xilinx"))
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